Low power memory device

Abstract

A memory device includes a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit includes a plurality of memory cells, at least one bit line, and at least one column word line. The plurality of memory cells are arranged along a second direction different from the first direction. The at least one bit line is elongated along the second direction, and configured to transmit data of a selected memory cell. The at least one column word line is elongated along the second direction, and configured to control electrical connections between the memory cells and the at least one bit line, wherein the selected memory cell is selected by a corresponding word line and the at least one column word line.

1 . A memory device, comprising:
 a plurality of word lines elongated along a first direction; and   at least one memory unit comprising:
 a plurality of memory cells arranged along a second direction different from the first direction; 
 at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; 
 at least one column word line elongated along the second direction; and 
 a plurality of switches, each of the switches having a control terminal coupled to the at least one column word line, a first terminal coupled to at least one memory cell, and a second terminal coupled to the at least one bit line. 
   
     
     
         2 . The memory device of  claim 1 , wherein the selected memory cell is selected by a corresponding word line and the at least one column word line. 
     
     
         3 . The memory device of  claim 1 , wherein the plurality of switches are transistors. 
     
     
         4 . A memory device, comprising:
 a plurality of word lines elongated along a first direction; and   at least one memory unit comprising:
 a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising at least one memory cell; 
 at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; 
 at least one column word line elongated along the second direction; and 
 a plurality of column switches, each of the column switches having a control terminal coupled to the at least one column word line, a first terminal coupled to one of the memory cell groups, and a second terminal coupled to the at least one bit line. 
   
     
     
         5 . The memory device of  claim 4 , wherein the selected memory cell is selected by a corresponding word line and the at least one column word line. 
     
     
         6 . The memory device of  claim 4 , wherein the plurality of column switches are transistors. 
     
     
         7 . The memory device of  claim 4 , wherein the at least one memory unit further comprises:
 a plurality of row word lines elongated along the first direction; and   a plurality of row switches, each of the row switches having a control terminal coupled to a corresponding row word line;   wherein each of the row switches and a corresponding column switch are coupled between one of the memory cell groups and the at least one bit line in series.   
     
     
         8 . The memory device of  claim 7 , wherein the selected memory cell is selected by a corresponding word line, the at least one column word line and a corresponding row word line. 
     
     
         9 . The memory device of  claim 7 , wherein the plurality of column switches and the plurality of row switches are transistors. 
     
     
         10 . The memory device of  claim 7 , wherein the memory device comprises a plurality of the memory units arranged along the first direction, a predetermined number of the memory units form a memory block, the column word lines of the memory units are grouped to control the column switches of corresponding memory blocks respectively, and the row word lines of the memory units are grouped to control the row switches of corresponding memory blocks respectively. 
     
     
         11 . The memory device of  claim 4 , wherein the memory device comprises a plurality of the memory units arranged along the first direction, a predetermined number of the memory units form a memory block, and the column word lines of the memory units are grouped to control the column switches of corresponding memory blocks respectively. 
     
     
         12 . The memory device of  claim 1 , wherein the memory device comprises a plurality of the memory units arranged along the first direction, a predetermined number of the memory units form a memory block, and the column word lines of the memory units are grouped to control the switches of corresponding memory blocks respectively. 
     
     
         13 . A memory device, comprising:
 a plurality of memory blocks arranged along a first direction, each of the memory blocks comprising a plurality of memory units arranged along the first direction, each of the memory units comprising:
 a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising at least one memory cell; 
 at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; and 
 a plurality of switches, each of the switches having a first terminal coupled to one of the memory cell groups, a second terminal coupled to the at least one bit line and a control terminal; 
   a plurality of word lines elongated along the first direction;   a plurality of row word lines elongated along the first direction;   wherein each of the row word lines is coupled to the control terminals of the switches of corresponding memory cell groups of a corresponding memory block.   
     
     
         14 . The memory device of  claim 13 , wherein the selected memory cell is selected by a corresponding word line and a corresponding row word line. 
     
     
         15 . The memory device of  claim 13 , wherein the plurality of switches are transistors.