Resistive random-access memory and method for controlling resistive random-access memory

Abstract

A resistive random access memory (ReRAM) and a method for controlling the ReRAM are proposed. The method detects a temperature of the ReRAM and set a reference resistance of a sense amplifier of the ReRAM according to the temperature. In addition, the method adapts to temperature fluctuation by switching operating mode based on the temperature of the ReRAM to enhance the reliability of the ReRAM. The control method may include a self-adaptive write mechanism, which takes write errors and data retention errors under high temperature into consideration at the same time. The control method may include a self-adaptive error correcting code mechanism, which determines the number of write errors according to Write-and-Verify (WAV) of writing and chooses the ECC algorithm. The control method may include a programmable WAV mechanism, programmably dividing N steps of WAV into two parts, so as to facilitate a memory write speed.

What is claimed is: 
     
         1 . A resistive random access memory, comprising:
 a resistive memory array, comprising a plurality of resistive memory devices, wherein the resistive memory devices store data of different values by using different resistance states;   a sense amplifier, adapted to determine the resistance states of the resistive memory devices according to a reference resistance, so as to output the data stored in the resistive memory devices; and   a temperature sensor, adapted to detect a temperature of the resistive random access memory.   
     
     
         2 . The resistive random access memory as claimed in  claim 1 , wherein the resistive random access memory is coupled to a controller, and the controller sets the reference resistance according to the temperature. 
     
     
         3 . A method for controlling a resistive random access memory, comprising:
 detecting a temperature of the resistive random access memory; and   setting a reference resistance of a sense amplifier of the resistive random access memory according to the temperature.   
     
     
         4 . The method for controlling the resistive random access memory as claimed in  claim 3 , further comprising:
 when the temperature of the resistive random access memory is lower than a switching temperature, switching to a normal mode, and setting the reference resistance at a first resistance corresponding to the normal mode; and   when the temperature of the resistive random access memory is higher than the switching temperature, switching to a high temperature mode, and setting the reference resistance at a second resistance corresponding to the high temperature mode, wherein the first resistance is greater than the second resistance.   
     
     
         5 . The method for controlling the resistive random access memory as claimed in  claim 4 , further comprising:
 when a time duration that the temperature of the resistive random access memory is lower than the switching temperature reaches a preset length of time, switching to the normal mode and setting the reference resistance at the first resistance; and   when a time duration that the temperature of the resistive random access memory is higher than the switching temperature reaches the preset length of time, switching to the high temperature mode and setting the reference resistance at the second resistance.   
     
     
         6 . The method for controlling the resistive random access memory as claimed in  claim 4 , wherein if resistance drifting occurs in one of resistive memory devices that has a resistance greater than the second resistance in the resistive random access memory, the resistance of the resistive memory device is still greater than the second resistance after resistance drifting. 
     
     
         7 . The method for controlling the resistive random access memory as claimed in  claim 4 , further comprising an asymmetrical coding, wherein the asymmetrical coding comprises:
 when a data is to be written to the resistive random access memory, calculating a number of a bit value of the data;   if the number of the bit value is greater than a half of a length of the data, flipping each bit of the data and writing the data to the resistive random access memory; and   if the number of the bit value is less than a half of the length of the data, writing the data as it original is to the resistive random access memory, wherein the bit value is equal to 1 in the normal mode and equal to 0 in the high temperature mode.   
     
     
         8 . The method for controlling the resistive random access memory as claimed in  claim 7 , further comprising:
 when switching from a first mode to a second mode, reading all the data of the resistive random access memory by continuing using the reference value of the first mode, writing all the data back to the resistive random access memory according to the second mode, and then setting the reference resistance at a reference resistance corresponding to the second mode, wherein the first mode is one of the normal mode and the high temperature mode, and the second mode is the other of the normal mode and the high temperature mode.   
     
     
         9 . The method for controlling the resistive random access memory as claimed in  claim 3 , further comprising:
 when a data is to be written to the resistive random access memory, calculating a number of a bit value of the data;   if the number of the bit value is greater than a half of a length of the data, flipping each bit of the data and writing the data to the resistive random access memory; and   if the number of the bit value is less than a half of the length of the data, writing the data as it original is to the resistive random access memory.   
     
     
         10 . The method for controlling the resistive random access memory as claimed in  claim 9 , further comprising:
 if the number of the bit value is greater than a half of the length of the data, setting a flag bit; and   when the data is read from the resistive random access memory, if the flag bit is already set, flipping each bit of the data to restore the data.   
     
     
         11 . The method for controlling the resistive random access memory as claimed in  claim 9 , wherein when the temperature of the resistive random access memory is greater than a switching temperature, the bit value is equal to 0, and when the temperature of the resistive random access memory is lower than the switching temperature, the bit value is equal to 1. 
     
     
         12 . The method for controlling the resistive random access memory as claimed in  claim 3 , further comprising:
 writing a data to the resistive random access memory by using a write voltage;   detecting a number of errors when the data is written; and   if the number of errors exceeds a threshold, increasing the write voltage and repeating the preceding steps.   
     
     
         13 . The method for controlling the resistive random access memory as claimed in  claim 12 , wherein the data is coded with an error correcting code before being written to the resistive random access memory, and the threshold is equal to the number of errors that the error correcting code is able to correct. 
     
     
         14 . The method for controlling the resistive random access memory as claimed in  claim 3 , further comprising:
 coding a data with a first error correcting code, and writing the data to the resistive random access memory;   detecting a number of errors when the data is written; and   if the number of error exceeds a threshold corresponding to the first error correcting code, replacing the first error correcting code with a second error correcting code and repeating the preceding steps, wherein a number of errors that the second error correcting code is able to correct is greater than the number of errors that the first error correcting code is able to correct.   
     
     
         15 . The method for controlling the resistive random access memory as claimed in  claim 14 , wherein the threshold is a decreasing function of a number of a bit value of the data, and an upper limit of the threshold is the number of errors that the first error correcting code or the second error correcting code is able to correct. 
     
     
         16 . The method for controlling the resistive random access memory as claimed in  claim 15 , wherein the bit value is 0. 
     
     
         17 . The method for controlling the resistive random access memory as claimed in  claim 3 , further comprising:
 writing a data to the resistive random access memory by using a first write voltage set;   detecting a number of errors when the data is written;   if the number of errors is greater than a threshold, storing the data in a waiting register; and   if the waiting register is already full of data, writing all the data stored in the waiting register to the resistive random access memory by using a second write voltage set, wherein the second write voltage set is higher than the first write voltage set.   
     
     
         18 . A method for controlling a resistive random access memory, comprising:
 when a data is to be written to the resistive random access memory, calculating a number of a bit value of the data;   if the number of the bit value is greater than a half of a length of the data, flipping each bit of the data and writing the data to the resistive random access memory; and   if the number of the bit value is less than a half of the length of the data, writing the data as it original is to the resistive random access memory.   
     
     
         19 . A method for controlling a resistive random access memory,
 comprising:   writing a data to the resistive random access memory by using a write voltage;   detecting a number of errors when the data is written; and   if the number of errors exceeds a threshold, increasing the write voltage and repeating the preceding steps.   
     
     
         20 . A method for controlling a resistive random access memory, comprising:
 coding a data by using a first error correcting code, and writing the data to the resistive random access memory;   detecting a number of errors when the data is written; and   if the number of errors exceeds a threshold corresponding to the first error correcting code, replacing the first error correcting code with a second error correcting code and repeating the preceding steps, wherein the number of errors that the second error correcting code is able to correct is greater than the number of errors that the first error correcting code is able to correct.   
     
     
         21 . A method for controlling a resistive random access memory, comprising:
 writing a data to the resistive random access memory by using a first write voltage set;   detecting a number of errors when the data is written;   if the number of errors is greater than a threshold, storing the data in a waiting register; and   if the waiting register is already full of data, writing all the data stored in the waiting register to the resistive random access memory by using a second write voltage set, wherein the second write voltage set is higher than the first write voltage set.