Communicating via a mailbox interface of a processor

Abstract

In one embodiment, a processor includes: a core to execute instructions, the core including a plurality of mailbox storages and a trust table to store a trust indicator for each of the plurality of mailbox storages; a first core perimeter logic coupled to the core and including a first storage to store state information of the core when the core is in a low power state; and a second core perimeter logic coupled to the first core perimeter logic and the core, the second core perimeter logic including a second storage to store the state information of the core when the first core perimeter logic is in a low power state. Other embodiments are described and claimed.

What is claimed is: 
     
         1 . A processor comprising:
 a core to execute instructions, the core including a plurality of mailbox storages and a trust table to store a trust indicator for each of the plurality of mailbox storages, each of the plurality of mailbox storages to be associated with a thread;   a first core perimeter logic coupled to the core, the first core perimeter logic including a first storage to store state information of the core when the core is in a low power state; and   a second core perimeter logic coupled to the first core perimeter logic and the core, the second core perimeter logic including a second storage to store the state information of the core when the first core perimeter logic is in a low power state.   
     
     
         2 . The processor of  claim 1 , wherein each of the plurality of mailbox storages comprises:
 a data storage; and   a command/address storage.   
     
     
         3 . The processor of  claim 2 , wherein the core is to check a busy indicator of the command/address storage of a first mailbox storage and if the busy indicator is inactive, the core is to write data information to the data storage of the first mailbox storage and second information to the command/address storage of the first mailbox storage and activate the busy indicator. 
     
     
         4 . The processor of  claim 3 , wherein the core is to write the data information and the second information responsive to a microcode write command. 
     
     
         5 . The processor of  claim 4 , wherein the core is to access a trust indicator associated with the first mailbox storage and if the trust indicator is set, enable communication of the data information in the data storage of the first mailbox storage to one of the first core perimeter logic and the second core perimeter logic, if microcode that issued the microcode write command is trusted. 
     
     
         6 . The processor of  claim 5 , wherein the core is to raise a machine check exception if the microcode is not trusted. 
     
     
         7 . The processor of  claim 5 , wherein the microcode write command comprises an intra-die interconnect no operation command. 
     
     
         8 . The processor of  claim 1 , wherein the core includes a first converter to convert information stored in a first mailbox storage to a format for communication on an intra-die interconnect coupled between the core and the first core perimeter logic. 
     
     
         9 . The processor of  claim 8 , wherein the core includes a second converter to convert information stored in a second mailbox storage to a format for communication on a parallel interconnect coupled between the core and the second core perimeter logic. 
     
     
         10 . A machine-readable medium having stored thereon data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method comprising:
 determining, via a mailbox control logic of a core of a processor, a state of a busy indicator of a first mailbox storage of the core;   if the busy indicator state is inactive writing, via the mailbox control logic, data information and control information into the first mailbox storage and setting the busy indicator to an active state; and   determining whether a trust indicator associated with the first mailbox storage is active, and if so, sending at least a portion of the data information and the control information to one of a first core perimeter logic coupled to the core or a second core perimeter logic coupled to the core based on a value of a destination indicator of the control information.   
     
     
         11 . The machine-readable medium of  claim 10 , wherein the method further comprises causing the core to enter into a low power state, while the selected first core perimeter logic or the second core perimeter logic is to remain powered on. 
     
     
         12 . The machine-readable medium of  claim 10 , wherein the method further comprises:
 sending at least the portion of the data information and the control information to the first core perimeter logic, if selected, via a first interconnect coupled between the core and the first core perimeter logic and sending at least the portion of the data information and the control information to the second core perimeter logic, if selected, via a second interconnect coupled between the core and the second core perimeter logic.   
     
     
         13 . The machine-readable medium of  claim 12 , wherein the method further comprises converting the data information and the control information from a first format to a second format and thereafter sending the converted data information and the converted control information to the first core perimeter logic. 
     
     
         14 . The machine-readable medium of  claim 12 , wherein the method further comprises sending a no operation command with the data information and the control information to the first core perimeter logic, wherein the first core perimeter logic is to store the data information and the control information in a storage of the first core perimeter logic responsive to the no operation command, and an uncore coupled to the first interconnect is to report a global observation to the core responsive to the no operation command. 
     
     
         15 . The machine-readable medium of  claim 14 , wherein the first core perimeter logic is to store the data information and the control information in the storage responsive to the no operation command including an active prefetch indicator. 
     
     
         16 . The machine-readable medium of  claim 14 , wherein the method further comprises:
 storing the data information from the storage of the first core perimeter logic to a second storage of the second core perimeter logic before entry of the first core perimeter logic into a low power state; and   storing the data information to a memory coupled to the processor before entry of the second core perimeter logic into a low power state.   
     
     
         17 . The machine-readable medium of  claim 16 , wherein the method further comprises:
 restoring the data information from the memory to the second storage of the second core perimeter logic after the second core perimeter logic exits the low power state; and   restoring the data information from the second storage of the second core perimeter logic to the storage of the first core perimeter logic after the first core perimeter logic exits the low power state.   
     
     
         18 . A system comprising:
 a processor having a core to execute instructions, the core including a mailbox interface having a plurality of mailbox storages and a trust table to store a trust indicator for each of the plurality of mailbox storages, each of the plurality of mailbox storages to be associated with a thread, a core perimeter logic coupled to the core and including a first domain having a first storage to store state information of the core when the core is in a low power state and a second domain having a second storage to store the state information of the core when the first domain is in a low power state, a first interconnect to communicate between the mailbox interface and the first domain, and a second interconnect to communicate between the mailbox interface and the second domain; and   a dynamic random access memory (DRAM) coupled to the processor.   
     
     
         19 . The system of  claim 18 , wherein the core, if a busy indicator of a first mailbox storage is inactive, is to write information to the first mailbox storage and activate the busy indicator, responsive to a microcode write command. 
     
     
         20 . The system of  claim 19 , wherein the core is to determine whether a trust indicator associated with the first mailbox storage is active, and if so, send at least a portion of the information from the first mailbox storage to one of the first domain or the second domain, based on a value of a destination indicator of the information.