Vector processor configured to operate on variable length vectors with register renaming

Abstract

A computer processor is disclosed. The computer processor comprises a vector unit comprising a vector register file comprising at least one vector register to hold a varying number of elements. The number of architected vector registers in the vector register file differs from the number of physical vector registers in the vector register file.

What is claimed is: 
     
         1 . A computer processor, comprising:
 a vector unit comprising:
 a vector register file comprising at least one vector register to hold a varying number of elements, 
 wherein the number of architected vector registers in the vector register file differs from the number of physical vector registers in the vector register file. 
   
     
     
         2 . The computer processor of  claim 1 , wherein the number of architected vector registers in the vector register file is smaller than the number of physical vector registers in the vector register file. 
     
     
         3 . The computer processor of  claim 1 , wherein before the vector instruction is executed using the at least one vector register, the computer processor is configured to map an input architected vector register to a physical vector register of the at least one vector register, and the computer processor is configured to map an output architected vector register to an unused physical register of the at least one vector register. 
     
     
         4 . The computer processor of  claim 1 , wherein, when an exception occurs while executing the vector instruction, the computer processor is configured to obtain the original state of the computer processoris by rolling back a mapping of architected registers to physical registers to before the exception occurred. 
     
     
         5 . The computer processor of  claim 1 , wherein, when an exception occurs while executing the vector instruction, the computer processor is configured to preserve partial results of execution of the vector instruction to expose the partial results to an exeption handling mechanism. 
     
     
         6 . The computer processor of  claim 5 , wherein the computer processor is configured to preserve partial results of execution of the vector instruction by coping the contents of the output vector register to a different non-renamed vector register, and by freeing the output vector register. 
     
     
         7 . The computer processor of  claim 5 , wherein the computer processor is configured to prevent the output vector register from being freed immediately, and to provide exception handling code to access contents of the output vector register. 
     
     
         8 . The computer processor of  claim 7 , wherein the computer processor is configured to employ another architected register that maps to the output register. 
     
     
         9 . The computer processor of  claim 1 , wherein the computer processor is configured to employ a renaming mechanism that preserves mapping for output registers for at least one instruction. 
     
     
         10 . The computer processor of  claim 1 , wherein the computer processor is multi-threaded processor, wherein each thread has its own pool of vector registers for renaming. 
     
     
         11 . The computer processor of  claim 1 , wherein the computer processor is multi-threaded processor, wherein threads of the computer processor have a common pool of vector registers and registers are renamed from that pool. 
     
     
         12 . A method, comprising:
 holding, by a vector register file comprising at least one register of a computer processor, a varying number of elements, wherein the number of architected vector registers in the vector register file differs from the number of physical vector registers in the vector register file.   
     
     
         13 . The method of  claim 12 , wherein the number of architected vector registers in the vector register file is smaller than the number of physical vector registers in the vector register file. 
     
     
         14 . The method of  claim 12 , wherein before the vector instruction is executed using the at least one vector register,
 mapping, by the computer processor, an input vector register to a physical vector register of the at least one vector register, and   mapping, by the computer processor, an output vector register to an unused physical register of the at least one vector register.   
     
     
         15 . The method of  claim 12 , wherein, when an exception occurs while executing the vector instruction, obtaining, by the computer processor, the original state of the computer processoris by rolling back a mapping of architected registers to physical registers to before the exception occurred. 
     
     
         16 . The method of  claim 12 , wherein, when an exception occurs while executing the vector instruction, preserving, by the computer processor, partial results of execution of the vector instruction to expose the partial results to an exeption handling mechanism. 
     
     
         17 . The method of  claim 16 , further comprising:
 preserving, by the computer processor, the partial results of execution of the vector instruction by coping the contents of the output vector register to a different non-renamed vector register; and   freeing the output vector register.   
     
     
         18 . The method of  claim 12 , further comprising:
 preventing, by the computer processor, the output vector register from being freed immediately; and   providing exception handling code to access contents of the output vector register.   
     
     
         19 . The method of  claim 18 , further comprising employing, by the computer processor, another architected register that maps to the output register. 
     
     
         20 . The method of  claim 12 , further comprising employing, by the computer processor, a renaming mechanism that preserves mapping for output registers for at least one instruction.