Field effect transistor (fet) with self-aligned double gates on bulk silicon substrate, methods of forming, and related design structures

Abstract

At least one isolation trench formed in a layer stack including substrate, channel, and upper gate layers define a channel in the channel layer. Lateral etching from the isolation trench(es) can form lateral cavities in the substrate and upper gate layer to substantially simultaneously form self-aligned lower and upper gates. The lower gate undercuts the channel, the upper gate is narrower than the channel, and a source and a drain can be formed on opposed ends of the channel. As a result, source-drain capacitance and gate-drain capacitance can be reduced, increasing speed of the resulting FET.

What is claimed is: 
     
         1 . A field effect transistor (FET) comprising:
 an upper gate;   a lower gate below and substantially self-aligned with the upper gate;   a channel between a bottom of the upper gate and a top of the lower gate and having opposed ends extending beyond the bottom of the upper gate and the top of the lower gate, bottoms of the opposed ends of the channel being undercut by respective cavities that bound sides of the lower gate; and   a source on a top of a first of the opposed ends of the channel and a drain on a top of a second of the opposed ends of the channel.   
     
     
         2 . The FET of  claim 1 , wherein the channel includes a lower portion having a substantially trapezoidal cross section extending from a bottom of an upper portion of the channel, a bottom of the lower portion meeting and being of substantially identical dimension to the top of the lower gate, wider than a top of the lower portion, and narrower than a bottom of the upper portion. 
     
     
         3 . The FET of  claim 1 , wherein the FET is a JFET including a first junction between the upper gate and the channel, the upper gate and the channel have opposite doping, a second junction between the channel and the lower gate, and the second junction includes a layer of silicon germanium (SiGe). 
     
     
         4 . The FET of  claim 3 , wherein the channel includes alternating layers of a first semiconductor material and SiGe to form a plurality of quantum wells with a layer of SiGe on the bottom of the channel being shared as the layer for the second junction. 
     
     
         5 . The FET of  claim 1 , wherein the channel includes alternating layers of a first semiconductor material and a second semiconductor material to form a plurality of quantum wells. 
     
     
         6 . The FET of  claim 1 , wherein at least one of the upper gate and the lower gate includes a metal deposited on the channel, the channel includes a semiconductor material, and the at least one of the upper gate or the lower gate thereby includes a Schottky barrier. 
     
     
         7 . A design structure readable by a machine used in design, manufacture, or simulation of an integrated circuit, the design structure comprising:
 an upper gate;   a lower gate below and substantially self-aligned with the upper gate;   a channel between a bottom of the upper gate and a top of the lower gate and having opposed ends extending beyond the bottom of the upper gate and the top of the lower gate, bottoms of the opposed ends of the channel being undercut by respective cavities that bound sides of the lower gate; and   a source on a top of a first of the opposed ends of the channel and a drain on a top of a second of the opposed ends of the channel.   
     
     
         8 . The design structure of  claim 7 , wherein the design structure comprises a netlist. 
     
     
         9 . The design structure of  claim 7 , wherein the design structure resides on non-transitory storage medium as a data format used for an exchange of layout data of integrated circuits. 
     
     
         10 . The design structure of  claim 7 , wherein the design structure resides in a programmable gate array.