Apparatus and method for high voltage i/o electro-static discharge protection

Abstract

An electronics chip includes a charge pump and at least one high voltage (HV) electro-static discharge (ESD) module. The charge pump is configured to provide a predetermined voltage across a microphone. The devices described herein are implemented in a standard low voltage CMOS process and has a circuit topology that provides an inherent ESD protection level (when it is powered down), which is higher than the operational (predetermined) DC level. At least one high voltage (HV) electro-static discharge (ESD) module is coupled to the output of the charge pump. The HV ESD module is configured to provide ESD protection for the charge pump and a microelectromechanical system (MEMS) microphone that is coupled to the chip. The at least one HV ESD module includes a plurality of PMOS or NMOS transistors having at least one high voltage NWELL/DNWELL region formed within selected ones of the PMOS or NMOS transistors. The at least one high voltage NWELL/DNWELL region has a breakdown voltage sufficient to allow a low voltage process to be used to construct the chip and still allow the HV ESD module to provide ESD protection for the chip.

What is claimed is: 
     
         1 . An electronics chip comprising:
 a charge pump;   a high voltage (HV) electro-static discharge (ESD) module electrically coupled between an output of the charge pump and a ground, wherein the HV ESD is configured to provide an ESD protection; and   a charge pump filter electrically coupled to the output of the charge pump and configured to provide noise filtering for the charge pump, wherein a voltage is output from the charge pump filter.   
     
     
         2 . The electronics chip of  claim 1 , wherein the charge pump filter includes:
 a first transistor and a second transistor connected in series between the output of the charge pump and an output of the charge pump filter, wherein for each of the first and the second transistors, a gate is connected to a drain;   a first diode and a second diode connected in parallel with the first transistor, wherein the first diode and the second diode are in opposite directions;   a third diode and a fourth diode connected in parallel with the second transistor, wherein the third diode and the fourth diode are in opposite directions;   a first capacitor electrically coupled between a node between the first and second transistors and the ground; and   a second capacitor electrically coupled between the output of the charge pump filter and the ground.   
     
     
         3 . The electronics chip of  claim 1 , wherein the HV ESD module includes:
 a transistor electrically coupled between the output of the charge pump and the ground;   a capacitor and a resistor connected in series between the output of the charge pump and the ground; and   at least a diode electrically coupled between a node between the capacitor and the resistor and the ground,   wherein a gate of the transistor is coupled to the node between the capacitor and the resistor.   
     
     
         4 . The electronics chip of  claim 3 , wherein the transistor is a laterally diffused MOS transistor (LDMOS). 
     
     
         5 . The electronics chip of  claim 1 , wherein the HV ESD module includes stacked stages connected in series between the output of the charge pump and the ground. 
     
     
         6 . The electronics chip of  claim 5 , wherein each of the stacked stages includes a transistor, and wherein a gate of the transistor is connected to a source of the transistor. 
     
     
         7 . The electronics chip of  claim 5 , wherein each of the stacked stages includes a transistor, and a resistor connected in series with the transistor, wherein a gate of the transistor is connected to a source of the transistor. 
     
     
         8 . The electronics chip of  claim 5 , wherein each of the stacked stages includes a transistor, a capacitor, and a resistor, wherein the capacitor and the resistor are connected in series, wherein a combination of the capacitor and the resistor is connected in parallel with the transistor, and wherein a gate of the transistor is connected to a node between the capacitor and the resistor. 
     
     
         9 . The electronics chip of  claim 1 , wherein the stacked stages include three stages. 
     
     
         10 . The electronics chip of  claim 1 , wherein the charge pump and the HV ESD module are implemented in a low voltage CMOS process. 
     
     
         11 . A device comprising:
 a charge pump configured to provide a voltage;   a high voltage (HV) electro-static discharge (ESD) module electrically coupled between an output of the charge pump and a ground;   a charge pump filter electrically coupled to the output of the charge pump and configured to provide noise filtering for the charge pump; and   a microphone electrically coupled to an output of the charge pump filter;   wherein the HV ESD module is configured to provide ESD protection for the charge pump, the charge pump filter, and the microphone.   
     
     
         12 . The device of  claim 11 , wherein the microphone is a MEMS microphone. 
     
     
         13 . The device of  claim 11 , wherein the charge pump filter includes:
 a first transistor and a second transistor connected in series between the output of the charge pump and an output of the charge pump filter, wherein for each of the first and the second transistors, a gate is connected to a drain;   a first diode and a second diode connected in parallel with the first transistor, wherein the first diode and the second diode are in opposite directions;   a third diode and a fourth diode connected in parallel with the second transistor, wherein the third diode and the fourth diode are in opposite directions;   a first capacitor electrically coupled between a node between the first and second transistors and the ground; and   a second capacitor electrically coupled between the output of the charge pump filter and the ground.   
     
     
         14 . The device of  claim 11 , wherein the HV ESD module includes:
 a transistor electrically coupled between the output of the charge pump and the ground;   a capacitor and a resistor connected in series between the output of the charge pump and the ground; and   at least a diode electrically coupled between a node between the capacitor and the resistor and the ground,   wherein a gate of the transistor is coupled to the node between the capacitor and the resistor.   
     
     
         15 . The device of  claim 11 , wherein the HV ESD module includes stacked stages connected in series between the output of the charge pump and the ground. 
     
     
         16 . The device of  claim 15 , wherein each of the stacked stages includes a transistor, and wherein a gate of the transistor is connected to a source of the transistor. 
     
     
         17 . The device of  claim 15 , wherein each of the stacked stages includes a transistor, and a resistor connected in series with the transistor, wherein a gate of the transistor is connected to a source of the transistor. 
     
     
         18 . The device of  claim 15 , wherein each of the stacked stages includes a transistor, a capacitor, and a resistor, wherein the capacitor and the resistor are connected in series, wherein a combination of the capacitor and the resistor is connected in parallel with the transistor, and wherein a gate of the transistor is connected to a node between the capacitor and the resistor. 
     
     
         19 . The device of  claim 15 , wherein the stacked stages include three stages. 
     
     
         20 . The device of  claim 11 , wherein the charge pump and the HV ESD module are implemented in a low voltage CMOS process.