Method and apparatus for improving a load independent buffer

Abstract

Described herein are apparatus, system, and method for reducing electrical over-stress of transistors and for generating an output with deterministic duty cycle for load independent buffers. The apparatus comprises a feedback capacitor electrically coupled between an input terminal and an output terminal of a buffer; and a switch, electrically parallel to the feedback capacitor and operable to electrically short the feedback capacitor in response to a control signal, wherein the switch causes a deterministic voltage level on the input terminal.

What is claimed is: 
     
         1 . An apparatus comprises:
 a buffer including a plurality of drivers including first and second drivers, wherein the first driver comprises:
 a first transistor having a gate terminal to receive a input signal, a drain terminal coupled to an output node, and a source terminal coupled to a first reference node; 
 a second transistor coupled in series with the first transistor, the second transistor having a gate terminal to receive the input signal, a drain terminal coupled to the output node, and a source terminal coupled to a second reference node; 
 a first capacitor having at least one terminal coupled to one of the gate terminals of the first and second transistors; and 
 a first switch coupled to the capacitor and operable to degrade an electrical path through the first capacitor; and 
   wherein the second driver comprises:
 a third transistor having a gate terminal to receive the input signal, a drain terminal coupled to the output node, and a source terminal coupled to the first reference node; 
 a fourth transistor coupled in series with the first transistor, the second transistor having a gate terminal to receive the input signal, a drain terminal coupled to the output node, and a source terminal coupled to the second reference node; 
 a second capacitor having at least one terminal coupled to one of the gate terminals of the first and second transistors; and 
 a second switch coupled to the second capacitor and operable to degrade an electrical path through the second capacitor; and 
   a slew rate controller electrically coupled to the buffer, wherein the slew rate controller is to control the first and second switches.   
     
     
         2 . The apparatus of  claim 2 , wherein the first and third transistors are p-type transistors, and wherein the second transistor and fourth transistors are an n-type transistor. 
     
     
         3 . The apparatus of  claim 2 , wherein the first reference node is to provide a supply voltage which is higher than a supply voltage to be provided on the second reference node. 
     
     
         4 . The apparatus of  claim 1 , wherein the output node is coupled to a pad, which is to be coupled to a transmission media. 
     
     
         5 . An apparatus comprising:
 a buffer having an input and output; and   a capacitor and switch coupled between the input and output, wherein the switch is to switchably establish, using a slew rate controller, a feedback path between the input and output through the capacitor.   
     
     
         6 . The apparatus of  claim 5 , wherein the buffer comprises:
 a first transistor having a gate terminal coupled to the input, a drain terminal coupled to the output, and a source terminal coupled to a first reference node; and   a second transistor coupled in series with the first transistor, the second transistor having a gate terminal coupled to the input, a drain terminal coupled to the output, and a source terminal coupled to a second reference node.   
     
     
         7 . The apparatus of  claim 6 , wherein the first transistor is a p-type transistor, and wherein the second transistor is an n-type transistor. 
     
     
         8 . The apparatus of  claim 6 , wherein the first reference node is to provide a supply voltage which is higher than a supply voltage to be provided on the second reference node. 
     
     
         9 . The apparatus of  claim 5 , wherein the output is coupled to a pad, which is to be coupled to a transmission media. 
     
     
         10 . The apparatus of  claim 5 , wherein the buffer comprises an inverter. 
     
     
         11 . An apparatus comprising:
 a first transistor having a gate terminal to receive an input signal, a drain terminal coupled to an output node, and a source terminal coupled to a first reference node;   a second transistor coupled in series with the first transistor, the second transistor having a gate terminal to receive the input signal, a drain terminal coupled to the output node, and a source terminal coupled to a second reference node; and   a capacitor and switch coupled between the gate terminals, of the first and second transistors, and the output node, wherein the switch is to switchably establish, using a slew rate controller, a feedback path between the gate terminals and the output node through the capacitor.   
     
     
         12 . The apparatus of  claim 11 , wherein the first reference node is to provide a supply voltage which is higher than a supply voltage to be provided on the second reference node. 
     
     
         13 . The apparatus of  claim 11 , wherein the output node is coupled to a pad, which is to be coupled to a transmission media. 
     
     
         14 . An apparatus comprising:
 a first transistor having a gate terminal to receive an input signal, a drain terminal coupled to an output node, and a source terminal coupled to a first reference node;   a second transistor coupled in series with the first transistor, the second transistor having a gate terminal to receive the input signal, a drain terminal coupled to the output node, and a source terminal coupled to a second reference node;   a capacitor having at least one terminal coupled to one of the gate terminals of the first and second transistors; and   a switch, coupled to the capacitor, operable to degrade an electrical path through the capacitor.   
     
     
         15 . The apparatus of  claim 14 , wherein the first transistor is a p-type transistor, and wherein the second transistor is an n-type transistor. 
     
     
         16 . The apparatus of  claim 14 , wherein the output node is coupled to a pad, which is to be coupled to a transmission media. 
     
     
         17 . The apparatus of  claim 14 , wherein the first reference node is to provide a supply voltage which is higher than a supply voltage to be provided on the second reference node. 
     
     
         18 . The apparatus of  claim 14  comprises logic to control the switch. 
     
     
         19 . An apparatus comprising:
 a first transistor having a gate terminal to receive an input signal, a drain terminal coupled to an output node, and a source terminal coupled to a first supply node;   a second transistor coupled in series with the first transistor, the second transistor having a gate terminal to receive the input signal, a drain terminal coupled to the output node, and a source terminal coupled to a second supply node;   a first capacitor having at least one terminal coupled to one of the gate terminals of the first and second transistors;   a first switch coupled to the first capacitor and operable to degrade an electrical path through the first capacitor;   a second capacitor having at least one terminal coupled to one of the gate terminals of the first and second transistors; and   a second switch coupled to the second capacitor and operable to degrade an electrical path through the second capacitor.   
     
     
         20 . A system comprising:
 a liquid crystal display (LCD); and   an integrated circuit coupled to the LCD, the integrated circuit having a driver which includes:
 a buffer having an input and output; and 
 a capacitor and switch coupled between the input and output, wherein the switch is to switchably establish, by a slew rate controller, a feedback path between the input and output through the capacitor. 
   
     
     
         21 . The system of  claim 20 , wherein the output is coupled to a pad, which is to be coupled to a transmission media. 
     
     
         22 . An apparatus comprising:
 a buffer including:
 a first transistor having a gate terminal to receive an input signal, a drain terminal coupled to an output node, and a source terminal coupled to a first reference node; and 
 a second transistor coupled in series with the first transistor, the second transistor having a gate terminal to receive the input signal, a drain terminal coupled to the output node, and a source terminal coupled to a second reference node; and 
   a slew rate controller coupled to the buffer, the slew rate controller including:
 a capacitor having at least one terminal coupled to one of the gate terminals of the first and second transistors; and 
 a switch coupled to the capacitor and operable to degrade an electrical path through the capacitor 
   
     
     
         23 . The apparatus of  claim 22 , wherein the output node is coupled to a pad, which is to be coupled to a transmission media. 
     
     
         24 . The apparatus of  claim 22 , wherein the first reference node is to provide a supply voltage which is higher than a supply voltage to be provided on the second reference node. 
     
     
         25 . An apparatus comprising:
 means for a buffering an input signal received at an input node and generating an output signal on an output node; and   means to switchably establish a feedback path between the input and output nodes through a capacitor.   
     
     
         26 . The apparatus of  claim 25 , wherein the output node is coupled to a pad, which is to be coupled to a transmission media.