Step Drill Test Structure of Layer Depth Sensing on Printed Circuit Board

Abstract

A step drill test structure for a PCB and method for using the same is disclosed. In one embodiment, a test structure includes a drill path and a connection via. The drill path may include sensing pads on selected ones of a plurality of layers of the PCB (e.g., the non-surface layers). The sensing pads of a given drill path may be electrically conductive, while the remaining portion of the drill path is non-conductive. The sensing pads of each drill path may be electrically coupled to the connection via. The depth of a given layer at a particular drill path may be determined by drilling, using an electrically conductive drill bit, into the drill path and determining when an electrical connection is made between the drill bit and the connection via.

1 - 9 . (canceled) 
     
     
         10 . A printed circuit board (PCB) comprising:
 a plurality of conductive layers, wherein the plurality of conductive layers are separated from one another by one of a plurality of dielectric layers;   a first coupon, wherein the first coupon includes a connection via and a drill path each extending vertically through the PCB, and wherein the drill path includes, in selected ones of the plurality of layers, a sensing pad having a corresponding electrical connection to the connection via.   
     
     
         11 . The printed circuit board as recited in  claim 10 , further comprising a plurality of coupons, including the first coupon, wherein each of the coupons includes a corresponding connection via and a corresponding drill path having a corresponding plurality of sensing pads. 
     
     
         12 . The printed circuit board as recited in  claim 10 , wherein each of the sensing pads of the drill path is electrically conductive, and wherein remaining portions of the drill path external to the sensing pads are electrically non-conductive. 
     
     
         13 . The printed circuit board as recited in  claim 10 , wherein each of the sensing pads is substantially co-planer with its corresponding one of the plurality of layers. 
     
     
         14 . A method comprising:
 determining a depth of a selected one of a plurality of layers of a printed circuit board (PCB) at each of a plurality of coupons, wherein each of the plurality of coupons includes a connection via and a drill path having, in a subset of the plurality of layers, a corresponding sensing pad that is physically and electrically coupled to the connection via; and   generating a topographic map of the selected one of the plurality of layers based on the depth of the selected one of the plurality of layers as determined at each of the plurality of coupons.   
     
     
         15 . The method as recited in  claim 14 , wherein each of the plurality of coupons is centered about a location having a unique pair of coordinates along each of an x-axis and y-axis of the PCB, and wherein the ground via and the drill path of each of the plurality of coupons extends along a z-axis. 
     
     
         16 . The method as recited in  claim 14 , wherein each of the plurality of coupons includes a plurality of wires, wherein each of the plurality of wires is coupled between the connection via and a unique one of the plurality of sensing pads. 
     
     
         17 . The method as recited in  claim 14 , wherein determining the depth of the selected one of the plurality of layers at a given one of the plurality of coupons comprises:
 drilling, using an electrically conductive drill bit, into and along an axis of the drill path of a selected one of the plurality of coupons;   determining when the electrically conductive drill bit has made an electrical connection to the connection via, wherein the electrical connection to the connection via indicates that the electrically conductive drill bit has made physical contact to the drill path of the given one of the plurality of coupons.   
     
     
         18 . The method as recited in  claim 14 , further comprising generating a topographic map for each of the plurality of layers based on depths of the layers as determined at each of the plurality of coupons. 
     
     
         19 . The method as recited in  claim 14 , further comprising:
 drilling, using an electrically conductive drill bit, into and along an axis of the drill path of a selected one of the plurality of coupons;   detecting a first electrical connection between a first sensing pad in the selected coupon and the connection via, the first sensing pad being located on a first one of the plurality of layers;   recording a depth of the first sensing pad;   breaking the first electrical connection;   repeating said drilling, said detecting, said recording, and said breaking for sensing pads in each remaining one of the plurality of layers.   
     
     
         20 . The method as recited in  claim 14 , further comprising:
 removing conductive material in a selected one of a plurality of through-hole vias between a surface of the PCB and the selected one of the plurality of layers, wherein an amount of conductive material removed from the selected one of the plurality of through-hole vias is based in part on a depth indicated in the topographic map of the selected one of the plurality of layers.   
     
     
         21 . The printed circuit board as recited in  claim 11 , wherein each of the plurality of coupons is centered about a location having a unique pair of coordinates along each of an x-axis and y-axis of the PCB, and wherein the ground via and the drill path of each of the plurality of coupons extends along a z-axis. 
     
     
         22 . The printed circuit board as recited in  claim 11 , wherein each of the plurality of coupons includes a plurality of wires, wherein each of the plurality of wires is coupled between the connection via and a unique one of the plurality of sensing pads.