Technique for translating dependent instructions

Abstract

In response to determining an operation is a dependent operation, a mapper of a processor determines the source registers of the operation from which the dependent operation depends. The mapper translates the dependent operation to a new operation that uses as its source operands at least one of the determined source registers and a source register of the dependent operation. The new operation is independent of other pending operations and therefore can be executed without waiting for execution of other operations, thus reducing execution latency.

What is claimed is: 
     
         1 . A method comprising:
 decoding received instructions at an instruction pipeline into a plurality of operations including a first operation and a second operation;   in response to determining the first operation of the plurality of operations is dependent on the second operation, translating the first operation to a third operation, the third operation independent of the second operation; and   executing the third operation without waiting for execution of the second operation.   
     
     
         2 . The method of  claim 1 , wherein translating the first operation comprises substituting a first micro-operation of the first operation with a second micro-operation. 
     
     
         3 . The method of  claim 1 , wherein translating the first operation comprises replacing a first source operand of the first operation with a first source operand of the second operation. 
     
     
         4 . The method of  claim 3 , wherein translating the first operation comprises adding a second source operand of the second operation as a second source operand of the third operation. 
     
     
         5 . The method of  claim 4 , wherein translating the first operation comprises setting a source operand of the first operation as a third source operand of the third operation. 
     
     
         6 . The method of  claim 5 , wherein translating the first operation comprises setting a destination operand of the first operation as a destination operand of the third operation. 
     
     
         7 . The method of  claim 1 , wherein the first operation and the second operation represent add instructions of a first type that add a first number of addends and the third operation represents an add instruction of a second type that adds a second number of addends. 
     
     
         8 . The method of  claim 1 , wherein the first operation represents an add instruction, the second operation represents a multiply instruction, and the third operation represents a multiply accumulate instruction. 
     
     
         9 . The method of  claim 1 , wherein the first operation is a logical operation. 
     
     
         10 . A method, comprising:
 decoding instructions at an instruction pipeline of a processor to determine a first operation and a second operation; and   in response to determining the second operation is dependent on the first operation:
 translating the second operation to a third operation; and 
 scheduling the third operation for execution prior to or concurrent with execution of the first operation. 
   
     
     
         11 . The method of  claim 10 , where the second operation an integer add operation that adds a first number of addends and the third operation, when executed, adds a second number of addends greater than the first number of addends. 
     
     
         12 . The method of  claim 10 , where the first operation is a floating point multiply operation, the second operation is a floating point add instruction and the third operation, when executed, performs a multiply-accumulate operation. 
     
     
         13 . The method of  claim 10 , wherein the third operation includes the source operands of the first operation and at least one of the source operands of the second operation. 
     
     
         14 . A processor, comprising:
 a decode stage to decode a plurality of instructions into a plurality of operations including a first operation and a second operation; and   a mapper coupled to the decode stage to translate the second operation to a third operation in response to determining the second operation is dependent on the first operation.   
     
     
         15 . The processor of  claim 14 , further comprising a scheduler coupled to the mapper, the scheduler to translate operands of the third operation from architectural register to physical registers. 
     
     
         16 . The processor of  claim 14 , further comprising a set of execution units coupled to the mapper to execute the third operation before or concurrent with the first operation. 
     
     
         17 . The processor of  claim 14 , wherein the mapper translates the second operation by replacing a first micro-operation of the second operation with a second micro-operation. 
     
     
         18 . The processor of  claim 14 , wherein the mapper translates the second operation by replacing a first source operand of the second operation with a first source operand of the first operation. 
     
     
         19 . The processor of  claim 18 , wherein the mapper translates the second operation by adding a second source operand of the first operation as a second source operand of the third operation. 
     
     
         20 . The processor of  claim 19 , wherein the mapper translates the second operation by setting a source operand of the second operation as a third source operand of the third operation.