High Speed And Low Power Sense Amplifier

Abstract

An improved sensing circuit is disclosed that utilizes a bit line in an unused memory array to provide reference values to compare against selected cells in another memory array. A circuit that can perform a self-test for identifying bit lines with leakage currents about an acceptable threshold also is disclosed.

What is claimed is: 
     
         1 . A sensing circuit for use in a memory device, comprising:
 a first array of memory cells comprising a selected memory cell corresponding to a word line and a first bit line;   a second array of memory cells comprising a plurality of memory cells corresponding to a second bit line;   a sensing circuit comprising a pre-charge circuit associated with the plurality of memory cells and a comparator with a first input and a second input and an output,   wherein the first input is determined by the value stored in the selected memory cell and the second input is determined by the second pre-charge circuit and the output of the comparator indicates the value stored in the selected memory cell.   
     
     
         2 . The circuit of  claim 1 , wherein the first array and the second array are symmetrical. 
     
     
         3 . The circuit of  claim 1 , wherein the pre-charge circuit comprises parasitic capacitance that stores a voltage. 
     
     
         4 . A sensing circuit for use in a memory device, comprising:
 a first array of memory cells comprising a selected memory cell corresponding to a word line and a first bit line;   a second array of memory cells comprising a plurality of memory cells corresponding to the first bit line;   a sensing circuit comprising a pre-charge circuit associated with the plurality of memory cells and a comparator with a first input and a second input and an output,   wherein the first input is determined by the value stored in the selected memory cell and the second input is determined by the pre-charge circuit and the output of the comparator indicates the value stored in the selected memory cell.   
     
     
         5 . The circuit of  claim 4 , wherein the first array and the second array are symmetrical. 
     
     
         6 . The circuit of  claim 4 , wherein the pre-charge circuit comprises parasitic capacitance that stores a voltage. 
     
     
         7 . A method of reading a selected memory cell, comprising:
 activating a word line and a first bit line in a first array of memory cells to read a selected memory cell;   activating a second bit line in a second array of memory cells;   applying a pre-charge voltage to a first node associated with the second bit line;   generating a voltage on a second node in response to a bit value stored in the selected memory cell;   comparing a voltage of the first node and a voltage of the second node to determine the bit value stored in the selected memory cell.   
     
     
         8 . The method of  claim 7 , wherein the first array and the second array are symmetrical. 
     
     
         9 . The method of  claim 7 , wherein the pre-charge circuit comprises parasitic capacitance that stores a voltage. 
     
     
         10 . A system for detecting leakage current associated with a bit line in a memory system, comprising
 a first circuit for generating a reference current;   a second circuit that generates leakage current associated with the bit line;   a first node coupled to the first circuit and second circuit;   a second node that exhibits a constant voltage;   a comparator that comprises the first node as an input and the second node as an input, wherein an output of the comparator indicates if the leakage current exceeds the reference current.   
     
     
         11 . The system of  claim 10 , wherein the reference current is a level of acceptable leakage current for the bit line. 
     
     
         12 . The memory system of  claim 10 , further comprising a controller. 
     
     
         13 . The memory system of  claim 12 , wherein the controller is configured to store an identifier of the bit line. 
     
     
         14 . A method of detecting leakage current associated with a bit line in a memory system, comprising
 generating a reference current at a first node;   generates a leakage current associated with the bit line at the first node;   generating a constant voltage at a second node;   comparing a voltage of the first node and a voltage of the second node and generating an output voltage that indicates if the leakage current exceeds the reference current.   
     
     
         15 . The method of  claim 14 , wherein the reference current is a level of acceptable leakage current for the bit line. 
     
     
         16 . The method of  claim 15 , further identifying the bit line. 
     
     
         17 . The method of  claim 16 , further comprising storing in a controller an identifier of the bit line. 
     
     
         18 . The method of  claim 16 , further comprising substituting a second bit line for the bit line during operation of the memory system. 
     
     
         19 . The method of  claim 14 , wherein the memory system comprises a first array of memory cells and a second array of memory cells. 
     
     
         20 . The method of  claim 14 , wherein the bit line is within the first array of memory cells.