Systems And Methods For Enhancing Performance Of A Coprocessor

Abstract

Techniques for minimizing coprocessor “starvation,” and for effectively scheduling processing in a coprocessor for greater efficiency and power. A run list is provided allowing a coprocessor to switch from one task to the next, without waiting for CPU intervention. A method called “surface faulting” allows a coprocessor to fault at the beginning of a large task rather than somewhere in the middle of the task. DMA control instructions, namely a “fence,” a “trap” and a “enable/disable context switching,” can be inserted into a processing stream to cause a coprocessor to perform tasks that enhance coprocessor efficiency and power. These instructions can also be used to build high-level synchronization objects. Finally, a “flip” technique is described that can switch a base reference for a display from one location to another, thereby changing the entire display surface.

What is claimed is: 
     
         1 . A method for scheduling coprocessor contexts for processing in a coprocessor, comprising:
 a central processing unit (CPU) generating a run list comprising a list of coprocessor contexts for processing by the coprocessor without CPU intervention;   delivering the run list to a scheduler, the scheduler preparing the contexts on the run list for processing by the coprocessor, the coprocessor beginning to process a first context of the run list based on an order indicated in the run list;   while processing the first context, determining, by the coprocessor, that a switching event has occurred, the switching event comprising a page fault in the coprocessor processing the first context, a general protection fault in the coprocessor processing the first context, or a determination that there is not another item in the run list; and   switching, by the coprocessor, to a next context in the run list in response to the coprocessor determining that the switching event has occurred, the coprocessor switching to the next context independently of intervention from the CPU.   
     
     
         2 . A method according to  claim 1 , wherein the coprocessor is a graphics processing unit (GPU). 
     
     
         3 . The method of  claim 1 , further comprising:
 signaling the CPU with an interrupt signal when the coprocessor switches from one context in the run list to a next context in the run list, the CPU building a second run list for the coprocessor in response to the CPU receiving the interrupt signal from the coprocessor.   
     
     
         4 . The method of  claim 1 , further comprising:
 generating a second run list by the scheduler process, the second run list having a different order of contexts than the run list, whereby the scheduler process can initiate a change in the order of contexts to be processed by the coprocessor when processing contexts in the second run list.   
     
     
         5 . The method of  claim 4 , wherein a second context is placed in a location within the second run list such that the second context is not executed first within the second run list, and further comprising:
 determining to include a third context of the run list in the second run list because the third context is in a location within the second run list such that the first context is executed first within the second run list.   
     
     
         6 . The method of  claim 1 , further comprising:
 storing information regarding a history of coprocessor switches from context to context in a specified system memory location readable by the scheduler.   
     
     
         7 . The method of  claim 6 , wherein the system memory location readable by the scheduler is a history buffer available to said coprocessor only. 
     
     
         8 . The method of  claim 7 , wherein the history buffer comprises sufficient memory to store at least twice the amount of information required to store the run list. 
     
     
         9 . The method of  claim 7 , further comprising:
 specifying a coprocessor write pointer, which indicates a location in the history buffer where the coprocessor can write new information.   
     
     
         10 . A computer readable device, wherein the computer readable device is not a signal, comprising computer executable instructions that when executed on a computer, cause the computer to perform operations comprising:
 a central processing unit (CPU) generating a run list comprising a list of coprocessor contexts for processing by a coprocessor without CPU intervention;   delivering the run list to a scheduler, the scheduler preparing the contexts on the run list for processing by the coprocessor, the coprocessor beginning to process a first context of the run list based on an order indicated in the run list;   while processing the first context, determining, by the coprocessor, that a switching event has occurred, the switching event comprising a page fault in the coprocessor processing the first context, a general protection fault in the coprocessor processing the first context, or a determination that there is not another item in the run list; and   switching, by the coprocessor, to a next context in the run list in response to the coprocessor determining that the switching event has occurred, the coprocessor switching to the next context independently of intervention from the CPU.   
     
     
         11 . A system, comprising:
 a processor;   a coprocessor;   a scheduler; and   a memory communicatively coupled to the processor when the system is operational, the memory bearing processor-executable instructions that, when executed on the processor, cause the system at least to:   cause the processor to generate a run list comprising a list of coprocessor contexts for processing by the coprocessor;   deliver the run list to the scheduler, the scheduler preparing the contexts on the run list for processing by the coprocessor, the coprocessor beginning to process a first context of the run list based on an order indicated in the run list;   while processing the first context, determine, by the coprocessor, that a switching event has occurred, the switching event comprising a page fault in the coprocessor processing the first context, a general protection fault in the coprocessor processing the first context, or a determination that there is not another item in the run list; and   switch, by the coprocessor, to a next context in the run list in response to the coprocessor determining that the switching event has occurred, the coprocessor switching to the next context independently of intervention from the processor.   
     
     
         12 . The system of  claim 11 , wherein the memory further bears processor-executable instructions that, when executed on the processor, cause the system at least to:
 signal the processor with an interrupt signal when the coprocessor switches from one context in the run list to a next context in the run list, the processor building a second run list for the coprocessor in response to the processor receiving the interrupt signal from the coprocessor.   
     
     
         13 . The system of  claim 11 , wherein the memory further bears processor-executable instructions that, when executed on the processor, cause the system at least to:
 generating a second run list by the scheduler process, the second run list having a different order of contexts than the run list, whereby the scheduler process can initiate a change in the order of contexts to be processed by the coprocessor when processing contexts in the second run list.   
     
     
         14 . The system of  claim 13 , wherein a second context is placed in a location within the second run list such that the second context is not executed first within the second run list, and wherein the memory further bears processor-executable instructions that, when executed on the processor, cause the system at least to:
 determine to include a third context of the run list in the second run list because the third context is in a location within the second run list such that the second context is executed first within the second run list.   
     
     
         15 . The computer-readable device of  claim 11 , further comprising computer executable instructions that when executed on the computer, cause the computer to perform operations comprising:
 storing information regarding a history of coprocessor switches from context to context in a specified system memory location readable by the scheduler.   
     
     
         16 . The computer-readable device of  claim 11 , wherein a system memory location readable by the scheduler is a history buffer available to said coprocessor only. 
     
     
         17 . The computer-readable device of  claim 16 , wherein the history buffer comprises sufficient memory to store at least twice the amount of information required to store the run list. 
     
     
         18 . The computer-readable device of  claim 11 , wherein the page fault in the coprocessor processing the first context comprises:
 a page fault that occurs to a context that references an invalid ring buffer or an invalid DMA buffer.