Data integrated circuit and display device including the same

Abstract

Provided is a data integrated circuit including: a data driving circuit, a shift register configured to output a plurality of latch clock signals, a latch configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals, and a clock generator configured to divide a main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch. At least two of the latch output signals are activated at different time intervals

What is claimed is: 
     
         1 . A data integrated circuit comprising:
 a shift register configured to output a plurality of latch clock signals;   a latch circuit configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals; and   a clock generator configured to divide a main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch,   wherein at least two of the latch output signals are activated at different time intervals.   
     
     
         2 . The data integrated circuit of  claim 1 , wherein each of the latch output signals has a different phase difference. 
     
     
         3 . The data integrated circuit of  claim 2 , wherein the latch circuit comprises a plurality of latch groups having at least one latch. 
     
     
         4 . The data integrated circuit of  claim 3 , wherein each latch group simultaneously outputs a subset of the digital image signals. 
     
     
         5 . The data integrated circuit of  claim 3 , wherein at least two of the latch groups simultaneously output a subset of the digital image signals in response to a latch output signal having the same phase. 
     
     
         6 . The data integrated circuit of  claim 1 , wherein the clock generator determines an activation state of each of the latch output signals in response to an external output control signal. 
     
     
         7 . The data integrated circuit of  claim 6 , wherein the clock generator performs a control to sequentially activate the latch output signals in response to the output control signal. 
     
     
         8 . The data integrated circuit of  claim 6 , wherein the clock generator performs a control to simultaneously activate at least two of the latch output signals in response to the output control signal. 
     
     
         9 . The data integrated circuit of  claim 1 , wherein the clock generator adjusts a phase difference between the latch output signals in response to an external delay signal. 
     
     
         10 . A display device comprising:
 a timing controller configured to output a main clock signal; and   a data driving circuit including a plurality of data integrated circuits outputting a plurality of data voltages based on the main clock signal,   wherein each data integrated circuit comprises:   a shift register configured to output a plurality of latch clock signals;   a latch circuit configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals; and   a clock generator configured to divide the main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch,   wherein at least two of the latch output signals are activated at different time intervals.   
     
     
         11 . The display device of  claim 10 , wherein the timing controller further outputs an output control signal and the clock generator performs a control that causes the latch output signals to have respectively different phases in response to the output control signal. 
     
     
         12 . The display device of  claim 10 , wherein the timing controller further outputs an output control signal and the clock generator outputs at least two of the latch output signals having the same phase among the latch output signals. 
     
     
         13 . The display device of  claim 10 , wherein the timing controller further outputs a delay signal and the clock generator adjusts a phase difference between the latch output signals in response to the delay signal. 
     
     
         14 . The display device of  claim 10 , wherein the latch circuit comprises a plurality of latch groups having at least one latch and each latch group simultaneously outputs a subset of the digital image signals. 
     
     
         15 . The display device of  claim 10 , wherein the clock generator outputs the latch output signals in a direction from both ends of the each data integrated circuit to one point of a left or right on the basis of a center part of the each data integrated circuit. 
     
     
         16 . A data integrated circuit comprising:
 a shift register configured to output a plurality of latch clock signals;   a latch circuit configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals; and   a clock generator configured to generate a plurality of latch output signals from a main clock signal and output the plurality of latch output signals to the latch,   wherein the main clock signal is active during an entire period, and   wherein each latch output signal is active during part of the period and inactive during a part of the period.   
     
     
         17 . The data integrated circuit of  claim 16 , wherein the latch circuit outputs a first image signal among the image signals when a first latch output signal among the latch output signals is active, and the latch circuit does not output the first output image signal when the first latch output signal is inactive. 
     
     
         18 . The data integrated circuit of  claim 16 , wherein a phase difference is present between the latch output signals. 
     
     
         19 . The data integrated circuit of  claim 16 , wherein the clock generator is configured to receive a control signal that indicates the phase difference. 
     
     
         20 . The data integrated circuit of  claim 19 , wherein the control signal includes a two bit value that represents the phase difference.