Semiconductor device with transistor local interconnects

Abstract

A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.

1 - 20 . (canceled) 
     
     
         21 . A semiconductor device comprising:
 a semiconductor substrate;   a plurality of transistors formed on the semiconductor substrate, each of the transistors comprising a source, a drain, and a gate;   a trench silicide layer electrically connecting one of the source or the drain of one of the transistors to one of the source or the drain of another of the transistors;   a CA layer electrically connected to the trench silicide layer; and   a CB layer electrically connected to a gate of one of the transistors and the CA layer.   
     
     
         22 . The semiconductor device as set forth in  claim 21 , wherein the trench silicide layer is sandwiched between the CA layer and the source or the drain of the transistor. 
     
     
         23 . The semiconductor device as set forth in  claim 21 , wherein the trench silicide layer is formed in a trench within a dielectric over the substrate. 
     
     
         24 . The semiconductor device as set forth in  claim 21 , wherein the salicide material comprises a metal chosen from nickel, cobalt, or tungsten. 
     
     
         25 . The semiconductor device as set forth in  claim 21 , wherein an upper surface of the CA layer and CB layer are generally level with one another with respect to the substrate. 
     
     
         26 . The semiconductor device as set forth in  claim 25 , further comprising a plurality of vias disposed over the CA or CB layers to selectively provide electrical connections to the respective CA or CB layers. 
     
     
         27 . The semiconductor device as set forth in  claim 26 , further comprising a metal layer disposed over the plurality of vias, wherein the plurality of vias provide electrical connections between the respective CA or CB layers and the metal layer. 
     
     
         28 . The semiconductor device as set forth in  claim 21 , wherein the plurality of transistors comprises a first transistor and a second transistor, and wherein the trench silicide layer electrically connects the source or the drain of the first transistor to the source or the drain of the second transistor. 
     
     
         29 . The semiconductor device as set forth in  claim 28 , wherein the first transistor is an n-type FET and the second transistor is a p-type FET. 
     
     
         30 . The semiconductor device as set forth in  claim 29 , wherein the drains of the transistors are electrically connected to one another via the trench silicide layer. 
     
     
         31 . The semiconductor device as set forth in  claim 30 , wherein the trench silicide layer does not cross over the gates while still electrically connecting the drains of the transistors. 
     
     
         32 . The semiconductor device as set forth in  claim 28 , wherein the gate of the first transistor and the gate of the second transistor are formed from a common linear strip. 
     
     
         33 . The semiconductor device as set forth in  claim 28 , wherein
 the gate of the first transistor extends linearly with the gate of the second transistor; and   the trench silicide layer is disposed on one side of the gates.   
     
     
         34 . The semiconductor device as set forth in  claim 21 , wherein the CA and CB layers are utilized to produce a scan-D flip-flop cell. 
     
     
         35 . A method of forming a semiconductor device, wherein the method comprises:
 providing a semiconductor substrate;   forming a plurality of transistors formed on the semiconductor substrate, each of the transistors comprising a source, a drain, and a gate;   forming a trench silicide layer electrically connecting one of the source or the drain of one of the transistors to one of the source or the drain of another of the transistors;   forming a CA layer electrically connected to the trench silicide layer and a CB layer electrically connected to a gate of one of the transistors and the CA layer.   
     
     
         36 . A method of forming a semiconductor device as set forth in  claim 35 , wherein an upper surface of the CA layer and the CB layer are generally level with one another with respect to the substrate, and wherein the method further comprises forming a metal layer over the CA layer and the CB to electrically connect the CA layer and the CB layer. 
     
     
         37 . A method of forming a semiconductor device as set forth in  claim 35 , further comprising depositing a dielectric over the transistors prior to forming the trench silicide layer. 
     
     
         38 . A method of forming a semiconductor device as set forth in  claim 37 , further comprising cutting a trench in the dielectric to the depth of the source or the drain of the transistors. 
     
     
         39 . A method of forming a semiconductor device as set forth in  claim 38  wherein forming the trench silicide layer comprises filling the trench with a metal. 
     
     
         40 . A semiconductor device comprising:
 a semiconductor substrate;   a plurality of transistors formed on the semiconductor substrate, each of the transistors comprising a source, a drain, and a gate;   a trench silicide layer electrically connecting one of the source or the drain of one of the transistors to one of the source or the drain of another of the transistors;   a CA layer electrically connected to the trench silicide layer, wherein the trench silicide layer is sandwiched between the CA layer and the source or the drain of the transistor;   a CB layer electrically connected to a gate of one of the transistors and the CA layer;   a plurality of vias disposed over the CA or CB layers to selectively provide electrical connections to the respective CA or CB layers; and   a metal layer disposed over the plurality of vias, wherein the plurality of vias provide electrical connections between the respective CA or CB layers and the metal layer.