Nonvolatile semiconductor memory device and method of manufacturing the same

Abstract

One embodiment includes: a substrate; a memory cell array that extends in a direction vertical to the substrate and includes a memory string having a plurality of series-coupled memory cells, and a selection transistor coupled to one end of the memory string; a wiring portion that includes a plurality of first conducting layers and a plurality of interlayer insulating films, the first conducting layers functioning as gate electrodes of the memory cell and the selection transistor, the interlayer insulating film being positioned between the first conducting layers in above and below directions; and a second conducting layer arranged on end portions of the plurality of first conducting layers of the selection transistor. The first conducting layers are electrically coupled in common to the second conducting layer.

What is claimed is: 
     
         1 . A nonvolatile semiconductor memory device, comprising:
 a substrate;   a memory cell array extending in a direction vertical to the substrate, the memory cell array including: a memory string having a plurality of series-coupled memory cells; and a selection transistor coupled to one end of the memory string;   a wiring portion that includes a plurality of first conducting layers and a plurality of interlayer insulating films, the first conducting layers functioning as gate electrodes of the memory cells and the selection transistor, the interlayer insulating film being positioned between the first conducting layers in above and below directions; and   a second conducting layer arranged on end portions of the plurality of first conducting layers included in the selection transistor, wherein   the plurality of first conducting layers included in the selection transistor is electrically coupled in common to the second conducting layer.   
     
     
         2 . The nonvolatile semiconductor memory device according to  claim 1 , wherein
 the plurality of first conducting layers included in the selection transistor have end portions aligned in a longitudinal direction of the first conducting layers, and   the plurality of first conducting layers whose end portions are aligned in the longitudinal direction are electrically coupled in common to one of the second conducting layer.   
     
     
         3 . The nonvolatile semiconductor memory device according to  claim 1 , wherein
 the plurality of first conducting layers included in the selection transistor have end portions forming a staircase structure,   the staircase structure of the plurality of first conducting layers has an end portion where the second conducting layer is arranged for each step, and   the first conducting layers having identical steps are electrically coupled in common to the second conducting layer, and the first conducting layers having mutually different steps are electrically independent from one another.   
     
     
         4 . The nonvolatile semiconductor memory device according to  claim 1 , wherein
 the plurality of first conducting layers included in the selection transistor have end portions projecting in a longitudinal direction of the first conducting layers with respect to end portions of the interlayer insulating films, and   the second conducting layer extends from the end portions of the first conducting layers to portions between the first conducting layers.   
     
     
         5 . The nonvolatile semiconductor memory device according to  claim 1 , wherein
 the selection transistor includes at least one dummy cell.   
     
     
         6 . The nonvolatile semiconductor memory device according to  claim 1 , wherein
 the first conducting layer and the second conducting layer are made of mutually different materials.   
     
     
         7 . The nonvolatile semiconductor memory device according to  claim 1 , wherein
 the selection transistor is a drain-side selection transistor coupled to an upper end of the memory string.   
     
     
         8 . The nonvolatile semiconductor memory device according to  claim 7 , further comprising
 a source-side selection transistor arranged between a lower end of the memory string and the substrate, the source-side selection transistor having the plurality of first conducting layers as gate electrodes thereof, wherein   the first conducting layers included in the source-side selection transistor have end portions where the second conducting layer is arranged, the first conducting layers included in the source-side selection transistor being electrically coupled in common to the second conducting layer.   
     
     
         9 . A method of manufacturing a nonvolatile semiconductor memory device, wherein
 the nonvolatile semiconductor memory device includes: a memory string having a plurality of series-coupled memory cells; and a selection transistor coupled to one end of the memory string, and   the manufacturing method comprises:   alternately laminating a plurality of first conducting layers and a plurality of interlayer insulating films on a substrate, the first conducting layers functioning as gate electrodes of the memory cells and the selection transistor, the interlayer insulating films being positioned between the first conducting layers in above and below directions; and   forming a second conducting layer on end portions of the plurality of first conducting layers included in the selection transistor, such that the plurality of first conducting layers included in the selection transistor is electrically coupled in common to the second conducting layer.   
     
     
         10 . The manufacturing method of the nonvolatile semiconductor memory device according to  claim 9 , further comprising:
 forming a void between the end portions of the plurality of first conducting layers by etching end portions of the interlayer insulating films between the plurality of first conducting layers; and   forming the second conducting layer on the end portions of the first conducting layers and inside the void.   
     
     
         11 . The manufacturing method of the nonvolatile semiconductor memory device according to  claim 9 , further comprising:
 forming the end portions of the plurality of first conducting layers included in the selection transistor in a staircase pattern;   forming the second conducting layer on end portions of the plurality of first conducting layers for each step of the staircase structure; and   electrically coupling the first conducting layers having identical steps in common to the second conducting layer, and electrically separating the first conducting layers having mutually different steps from one another.   
     
     
         12 . The manufacturing method of the nonvolatile semiconductor memory device according to  claim 9 , wherein
 the selection transistor include at least one dummy cell.   
     
     
         13 . The manufacturing method of the nonvolatile semiconductor memory device according to  claim 9 , wherein
 the first conducting layer is a metal film formed in a void caused by removing a sacrifice film laminated alternately with the interlayer insulating films by etching, and   the second conducting layer is formed after the metal film is formed.   
     
     
         14 . The manufacturing method of the nonvolatile semiconductor memory device according to  claim 9 , wherein
 the first conducting layer and the second conducting layer are made of mutually different materials.   
     
     
         15 . The manufacturing method of the nonvolatile semiconductor memory device according to  claim 9 , wherein
 the selection transistor is a drain-side selection transistor coupled to an upper end of the memory string.   
     
     
         16 . The manufacturing method of the nonvolatile semiconductor memory device according to  claim 15 , further comprising
 providing a source-side selection transistor arranged between a lower end of the memory string and the substrate, the source-side selection transistor having the plurality of first conducting layers as gate electrodes thereof, wherein   the first conducting layers included in the source-side selection transistor have end portions where the second conducting layer is arranged, the first conducting layers being electrically coupled in common to the second conducting layer.