Three-dimensional semiconductor memory device and method of fabricating the same

Abstract

A semiconductor memory device includes a stack including gate electrodes sequentially stacked on a substrate, a vertical insulating structure penetrating the stack vertically with respect to the gate electrodes, a vertical channel portion disposed on an inner side surface of the vertical insulating structure, and a common source region formed in the substrate and spaced apart from the vertical channel portion. A bottom region of the vertical channel portion has a protruding surface in contact with a bottom region of the vertical insulating structure.

What is claimed is: 
     
         1 . A semiconductor memory device, comprising:
 a stack including gate electrodes sequentially stacked on a substrate;   a vertical insulating structure penetrating the stack vertically with respect to the gate electrodes;   a vertical channel portion disposed on an inner surface of the vertical insulating structure; and   a common source region formed in the substrate and spaced apart from the vertical channel portion,   wherein a bottom region of the vertical channel portion has a protruding surface in contact with a bottom region of the vertical insulating structure.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein the protruding surface of the bottom region of the vertical channel portion has a curved profile. 
     
     
         3 . The semiconductor memory device of  claim 1 , wherein the protruding surface of the bottom region of the vertical channel portion has a vertical side profile. 
     
     
         4 . The semiconductor memory device of  claim 3 , wherein the protruding surface of the bottom region of the vertical channel portion is connected to a bottom surface of the bottom region of the vertical channel portion to form an angular profile. 
     
     
         5 . The semiconductor memory device of  claim 3 , wherein the protruding surface of the bottom region of the vertical channel portion is connected to a bottom surface of the bottom region of the vertical channel portion to form a curved profile. 
     
     
         6 . The semiconductor memory device of  claim 1 , wherein the bottom region of the vertical channel portion has a larger width than a top region of the vertical channel portion. 
     
     
         7 . The semiconductor memory device of  claim 1 , wherein the vertical insulating structure has a smaller width between the stack and the bottom region of the vertical channel portion than between the stack and a top region of the vertical channel portion. 
     
     
         8 . The device of  claim 1 , wherein the vertical channel portion comprises a first channel portion and a second channel portion disposed between the first channel portion and the vertical insulating structure,
 a top region of the vertical channel portion comprises an upper first channel portion of the first channel portion and the second channel portion, and   the bottom region of the vertical channel portion comprises a lower first channel portion of the first channel portion.   
     
     
         9 . The semiconductor memory device of  claim 1 , further comprising a lower channel protruding from the substrate in a vertical direction with respect to the gate electrodes and being in contact with the vertical channel portion,
 wherein a first portion of a top surface of the lower channel is in contact with a bottom surface of the vertical channel portion, and   a second portion of the top surface of the lower channel is in contact with a bottom surface of the vertical insulating structure.   
     
     
         10 . A semiconductor memory device, comprising:
 a stack including gate electrodes sequentially stacked on a substrate;   a vertical insulating structure penetrating the stack vertically with respect to the gate electrodes;   a vertical channel portion disposed on an inner surface of the vertical insulating structure; and   a common source region formed in the substrate and spaced apart from the vertical channel portion,   wherein the vertical channel portion comprises a first channel pattern and a second channel pattern, the first channel pattern partially covers an inner surface of the vertical insulating structure, and the second channel pattern includes an upper second channel pattern covering an inner surface of the first channel pattern and a lower second channel pattern disposed below the first channel pattern, and   an outer surface portion of the lower second channel pattern protrudes a bottom portion of the vertical insulating structure exposed by the first channel pattern and contacts the bottom portion of the vertical insulating structure exposed by the first channel pattern.   
     
     
         11 . The semiconductor memory device of  claim 10 , wherein a width of the lower second channel pattern is larger than a sum of widths of the upper second channel pattern and the first channel pattern. 
     
     
         12 . The semiconductor memory device of  claim 10 , wherein the vertical insulating structure comprises a plurality of layers,
 an outer surface of the first channel pattern is in contact with one of the layers of the vertical insulating structure, and   the outer surface portion of the lower second channel pattern is in contact with at least one of the layers of the vertical insulating structure.   
     
     
         13 . The semiconductor memory device of  claim 12 , wherein the vertical insulating structure comprises a first insulating layer, a second insulating layer, and a third insulating layer sequentially stacked on an inner surface of the stack,
 the outer surface of the first channel pattern is in contact with the third insulating layer, and   the outer surface portion of the lower second channel pattern is in contact with bottom portions of the first, second, and third insulating layers.   
     
     
         14 . The semiconductor memory device of  claim 10 , wherein the outer surface portion of the lower second channel pattern has a curved profile. 
     
     
         15 . The semiconductor memory device of  claim 10 , wherein a bottom surface of the first channel pattern is spaced apart from the lower second channel pattern. 
     
     
         16 . A semiconductor memory device, comprising:
 a stack including gate electrodes sequentially disposed on a substrate;   a vertical insulating structure penetrating the stack substantially perpendicularly with respect to the gate electrodes;   a vertical channel portion disposed on an inner surface of the vertical insulating structure and extending in a same direction as the vertical insulating structure; and   a common source region formed in the substrate and spaced apart from the vertical channel portion,   wherein a bottom region of the vertical channel portion includes an outer surface that is extended toward an outer surface of the vertical insulating structure and contacts the vertical insulating structure.   
     
     
         17 . The semiconductor memory device of  claim 16 , wherein the vertical channel portion includes a first channel pattern and a second channel pattern,
 wherein the first channel pattern is disposed on an inner surface of the vertical insulating structure, and the second channel pattern is disposed on an inner surface of the first channel pattern,   wherein the second channel pattern includes a lower second channel pattern and an upper second channel pattern disposed on the lower second channel pattern,   wherein a portion of an outer surface of the lower second channel pattern corresponds to the outer surface of the bottom region of the vertical channel portion that is extended toward the outer surface of the vertical insulating structure and contacts the vertical insulating structure.   
     
     
         18 . The semiconductor memory device of  claim 17 , wherein a first circumference of the first channel pattern decreases in a direction toward the substrate, and a second circumference of the second channel pattern decreases in the direction toward the substrate. 
     
     
         19 . The semiconductor memory device of  claim 17 , wherein a bottom portion of the first channel pattern contacts the lower second channel pattern. 
     
     
         20 . The semiconductor memory device of  claim 17 , wherein the portion of the outer surface of the lower second channel pattern includes a flat region.