US2016276411A1PendingUtilityA1

Addressable siox memory array with incorporated diodes

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Assignee: TOUR JAMES MPriority: Aug 26, 2011Filed: Jun 2, 2016Published: Sep 22, 2016
Est. expiryAug 26, 2031(~5.1 yrs left)· nominal 20-yr term from priority
H10D 8/422H10D 8/411H10D 8/60H10D 8/051H10D 8/045H01L 45/1233H01L 45/145H01L 29/872H01L 29/8613H01L 45/1608H01L 27/2463H01L 29/8611H01L 27/2409H10N 70/023H10N 70/883H10B 63/20H10N 70/063H10B 63/80H10N 70/20H10N 70/826H10N 70/026H10N 70/841H10N 70/021
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Claims

Abstract

Various embodiments of the resistive memory cells and arrays discussed herein comprise: (1) a first electrode; (2) a second electrode; (3) resistive memory material; and (4) a diode. The resistive memory material is selected from the group consisting of SiO x , SiO x N y , SiO x N y H, SiO x C z , SiO x C z H, and combinations thereof, wherein each of x, y and z are equal or greater than 1 or equal or less than 2. The diode may be any suitable diode, such as n-p diodes, p-n diodes, and Schottky diodes.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method of forming a resistive memory cell, wherein the method comprises:
 depositing doped silicon on a substrate, wherein the substrate is an insulating substrate;   depositing a first electrode on the insulating substrate;   depositing a diode;   depositing a resistive memory material, wherein the resistive memory material is selected from the group consisting of SiO x , SiO x H, SiO x N y , SiO x N y H, SiO x C z , SiO x C z H, and combinations thereof, wherein each of x, y and z are equal to or greater than 1 or equal to or less than 2; and   depositing a second electrode.   
     
     
         2 . The method of  claim 1 , wherein the resistive memory material is deposited on the first electrode; and the diode is deposited on the resistive memory material. 
     
     
         3 . The method of  claim 1 , wherein diode is deposited on the first electrode. 
     
     
         4 . The method of  claim 3 , further comprising depositing a metallic layer on the diode, wherein the resistive memory material is deposited on the metallic layer. 
     
     
         5 . The method of  claim 1 , wherein the first electrode is deposited on the doped silicon; and
 depositing a metallic layer on the doped silicon, wherein the resistive memory material is deposited on the metallic layer.   
     
     
         6 . The method of  claim 1 , wherein the diode is selected from the group consisting of n-p diodes, p-n diodes, and Schottky diodes.

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