US2016284671A1PendingUtilityA1

Integrated Circuit Assembly and Method of Making

53
Assignee: QUALCOMM SWITCH CORPPriority: Jul 15, 2009Filed: Jun 3, 2016Published: Sep 29, 2016
Est. expiryJul 15, 2029(~3 yrs left)· nominal 20-yr term from priority
Inventors:Michael A. StuberStuart B. MolinMark DruckerPeter Fowler
H10W 99/00H10W 90/26H10W 90/722H10W 72/0198H10W 72/075H10W 72/879H10W 90/754H10W 72/5524H10W 72/5522H10W 72/59H10W 90/753H10W 72/952H10W 72/29H10W 72/01935H10W 72/01938H10W 90/00H10W 72/30H10W 72/07533H10W 72/07337H10W 72/07336H10W 72/073H10W 72/07307H10W 72/07236H10W 72/07233H10W 72/072H10W 72/241H10W 72/07207H10W 80/327H10W 80/041H10W 80/211H10W 90/724H10W 72/252H10W 72/01235H10W 72/01238H10W 72/01225H10W 72/01223H10W 72/01204H10W 72/012H10P 90/1922H10P 72/7438H10P 72/7426H10P 72/7422H10P 72/744H10P 72/74H10W 10/181H10P 90/1914H10P 54/00H10W 74/15H10W 74/012H10W 72/5525H10W 90/701H10W 72/90H10W 72/50H10W 72/20H10W 40/228H10D 86/201H10D 84/85H10D 88/00H10D 86/01H10D 30/6758H10D 30/6704H01L 2224/0401H01L 27/1203H01L 2224/48091H01L 24/14H01L 25/0657H01L 2224/04042H01L 24/46H01L 24/06
53
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface. A first active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the first active layer and formed on the second surface of the insulating layer. A substrate having a first surface and a second surface, with a second active layer formed in the first surface, is provided such that the first active layer is coupled to the second surface of the substrate.

Claims

exact text as granted — not AI-modified
1 . An integrated circuit assembly comprising:
 an insulating layer having a first surface and a second surface;   a first active layer contacting the first surface of the insulating layer;   a metal bond pad formed on the second surface of the insulating layer;   wherein the metal bond pad is electrically coupled to the first active layer;   a substrate having a first surface and a second surface, the first active layer being coupled to the second surface of the substrate;   a second active layer formed on the first surface of the substrate;   a first singulated wafer portion including the insulating layer and the first active layer; and   a second singulated wafer portion bonded to the first singulated wafer portion, the second wafer singulated portion including the substrate and the second active layer.   
     
     
         2 . The integrated circuit assembly of  claim 1 , further comprising: a printed circuit board, the printed circuit board being electrically coupled to the metal bond pad. 
     
     
         3 . The integrated circuit assembly of  claim 2 , wherein the printed circuit board is electrically coupled with a solder bump to the first active layer. 
     
     
         4 . The integrated circuit assembly of  claim 2 , wherein the printed circuit board is electrically coupled to the second active layer through a wire bond. 
     
     
         5 . The assembly of  claim 2 , wherein the printed circuit board is electrically coupled with a solder bump to the second active layer. 
     
     
         6 . The assembly of  claim 2 , wherein the printed circuit board is electrically coupled to the first layer through a wire bond. 
     
     
         7 . The integrated circuit assembly of  claim 1 , wherein the substrate is less than 100 microns thick. 
     
     
         8 . The integrated circuit assembly of  claim 1 , wherein the substrate is less than 30 microns thick. 
     
     
         9 . The integrated circuit assembly of  claim 1 , wherein the integrated circuit assembly does not include a vertical electrical connection through the first singulated wafer portion and the second singulated wafer portion. 
     
     
         10 . The integrated circuit assembly of  claim 1 , wherein the first active layer or the second active layer includes passive devices. 
     
     
         11 . A singulated integrated circuit assembly comprising:
 a silicon on insulator (SOI) wafer portion including a first active layer formed on top of an insulating layer, the SOI wafer portion further including a first plurality of metal bond pads on a back side of the insulating layer, each of the metal bond pads of the first plurality of metal bond pads being in communication with active devices of the first active layer; and   a first wafer portion having a second active layer formed on top of a semiconductor substrate layer, the first wafer portion further including a second plurality of metal bond pads formed above the second active layer and being in communication with active devices of the second active layer, further wherein a back side of the first wafer portion is bonded to a top side of the SOI wafer portion.   
     
     
         12 . The singulated integrated circuit assembly of  claim 11 , further comprising:
 a plurality of solder bumps disposed on the first plurality of metal bond pads; and   a printed circuit board having a third plurality of metal bond pads in communication with the plurality of solder bumps.   
     
     
         13 . The singulated integrated circuit assembly of  claim 11 , further comprising:
 a plurality of solder bumps disposed on the second plurality of metal bond pads; and   a printed circuit board having a third plurality of metal bond pads in communication with the plurality of solder bumps.   
     
     
         14 . The singulated integrated circuit assembly of  claim 11 , further comprising:
 a first printed circuit board coupled with the first plurality of metal bond pads; and   a plurality of bonding wires coupling the second plurality of metal bond pads to the first printed circuit board.   
     
     
         15 . The singulated integrated circuit assembly of  claim 11 , further comprising:
 a first printed circuit board coupled with the second plurality of metal bond pads; and   a plurality of bonding wires coupling the first plurality of metal bond pads to the first printed circuit board.   
     
     
         16 . A singulated integrated circuit assembly comprising:
 a first wafer portion having a first active layer formed on top of a semiconductor substrate, the first wafer portion further including a first metal bond pad formed on a top side of the first wafer portion and coupled with a first active device of the first active layer; and   a second wafer portion having a second active layer formed on a top side of an insulator layer and having a second metal bond pad formed on a back side of the insulator layer, the second bond pad being in electrical communication with a second active device of the second active layer, further wherein a top side of the second wafer portion is bonded to a back side of the first wafer portion.   
     
     
         17 . The singulated integrated circuit assembly of  claim 11 , further comprising:
 a solder bump disposed on the first metal bond pad; and   a printed circuit board having a third metal bond pad in communication with the solder bump.   
     
     
         18 . The singulated integrated circuit assembly of  claim 11 , further comprising:
 a solder bump disposed on the second metal bond pad; and   a printed circuit board having a third metal bond pad in communication with the solder bump.   
     
     
         19 . The singulated integrated circuit assembly of  claim 11 , further comprising:
 a first printed circuit board coupled with the first metal bond pad; and   a bonding wire coupling the second metal bond pad to the first printed circuit board.   
     
     
         20 . The singulated integrated circuit assembly of  claim 11 , further comprising:
 a first printed circuit board coupled with the second metal bond pad; and   a bonding wire coupling the first metal bond pad to the first printed circuit board.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.