Gear Shifting From Binary Phase Detector to PAM Phase Detector in CDR Architecture

Abstract

A device and method for providing clock data recovery (CDR) in a receiver is disclosed. The method comprises receiving a Phase Amplitude Modulation (PAM) signal; on startup, using a non-return-to-zero (NRZ)-based phase frequency detector (PFD) to acquire signal frequency from the received PAM signal; and responsive to a determination, switching to a PAM phase detector (PD) for steady state operation.

What is claimed is: 
     
         1 . A method for providing clock data recovery (CDR) in a receiver, the method comprising:
 receiving a Phase Amplitude Modulation (PAM) signal;   on startup, using a non-return-to-zero (NRZ)-based phase frequency detector (PFD) to acquire a frequency from the received PAM signal; and   responsive to a determination, switching to a PAM phase detector (PD) for steady state operation of the CDR module.   
     
     
         2 . The method as recited in  claim 1  further comprising receiving at the NRZ-based PFD a first signal that comprises the received PAM signal after amplification and equalization using a continuous time linear filter. 
     
     
         3 . The method as recited in  claim 2  further comprising receiving at the PAM PD a second signal that comprises the first signal summed with a correction provided by a Decision Feedback Equalizer (DFE). 
     
     
         4 . The method as recited in  claim 1  further comprising making the determination responsive to detecting that a fixed time has elapsed since DFE convergence. 
     
     
         5 . A clock data recovery (CDR) module comprising:
 a non-return-to-zero (NRZ)-based phase frequency detector (PFD); and   a PAM phase detector (PAMPD), wherein the CDR module initiates phase and frequency acquisition using the NRZ-based PFD and responsive to a determination, switches to PAMPD for steady state operation.   
     
     
         6 . The CDR module as recited in  claim 5  wherein the NRZ-based PFD is connected to receive a first signal that comprises a received PAM signal that has been equalized by a linear equalizer and amplified by a voltage gain amplifier. 
     
     
         7 . The CDR module as recited in  claim 6  wherein the PAMPD is further connected to receive a second signal that comprises the first signal summed with a correction provided by a decision feedback equalizer (DFE). 
     
     
         8 . The CDR module as recited in  claim 5  wherein the determination is made responsive to detecting that a fixed time has elapsed since DFE convergence.