Providing code sections for matrix of arithmetic logic units in a processor

Abstract

The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.

1 . (canceled) 
     
     
         2 . A method to process loops in a processor, the method comprising:
 in a processor having a plurality of execution units:
 fetching instructions from an instruction memory; 
 detecting and analyzing loop code within the fetched instructions; 
 determining a portion of the loop code that is at least one of loop counter code and loop exit criterion code based on the analyzing; and 
 moving the determined portion of loop code to a dedicated loop code processing unit inside the processor. 
   
     
     
         3 . The method of  claim 2  wherein, during further processing of the loop code, the loop code processing unit counts iterations of a loop defined by the loop code, the counting based on the portion of the loop code. 
     
     
         4 . The method of  claim 2  wherein, during further processing of the loop code, the loop code processing unit compares data for determining a loop exit criterion. 
     
     
         5 . A processor comprising:
 at least one instruction fetch unit configured to fetch instructions from an instruction memory;   at least one loop code detector unit configured to detect loop code in the fetched instructions;   at least one loop code analyzer unit configured to analyze the detected loop code to determine at least one of loop counter code and loop exit criterion code;   at least one dedicated unit processing at least one of the loop counter code and loop exit criterion code; and   a plurality of execution units configured to execute the instructions.   
     
     
         6 . The processor of  claim 5  wherein the loop code processing unit comprises a loop iteration counter configured to count iterations of a loop defined by the loop code, the counting based on the loop counter code. 
     
     
         7 . The processor of  claim 5  wherein the loop code processing unit comprises a comparator determining a loop exit criterion of the loop code based on the loop exit criterion code.