Silicon solar cell and method of manufacturing the same

Abstract

A silicon solar cell and a method of manufacturing the same are disclosed. The silicon solar cell includes a silicon semiconductor substrate doped with first conductive impurities, an emitter layer doped with second conductive impurities having polarities opposite polarities of the first conductive impurities on the substrate, an anti-reflective layer on an entire surface of the substrate, an upper electrode that passes through the anti-reflective layer and is connected to the emitter layer, and a lower electrode connected to a lower portion of the substrate. The emitter layer includes a first emitter layer heavily doped with the second conductive impurities and a second emitter layer lightly doped with the second conductive impurities. A surface resistance of the second emitter layer is 100 Ohm/sq to 120 Ohm/sq.

What is claimed is: 
     
         1 . A method of manufacturing a silicon solar cell using a screen printing method comprising:
 providing a silicon semiconductor substrate doped with first conductive impurities;   forming an emitter layer doped with second conductive impurities on a front surface of the silicon semiconductor substrate, the second conductive impurities having polarities opposite polarities of the first conductive impurities;   forming an etching mask pattern using the screen printing method at a position where an upper electrode on the emitter layer is connected to the emitter layer;   forming a selective emitter layer having a first emitter layer heavily doped with the second conductive impurities and a second emitter layer lightly doped with the second conductive impurities by an etch-back process on the emitter layer using the etching mask pattern as a mask;   removing the etching mask pattern remaining after the etch-back process is performed;   forming an anti-reflective layer on the selective emitter layer;   forming the upper electrode on the first emitter layer to pass through the anti-reflective layer and connecting the upper electrode to the first emitter layer at a formation position of the upper electrode; and   forming a lower electrode to a lower portion of the silicon semiconductor substrate.   
     
     
         2 . The method of  claim 1 , wherein the first conductive impurities are p-type impurities and the second conductive impurities are n-type impurities. 
     
     
         3 . The method of  claim 1 , wherein forming the etching mask pattern comprises performing a screen printing process using a glass frit paste to form the etching mask pattern. 
     
     
         4 . The method of  claim 1 , wherein forming the etching mask pattern comprises performing a screen printing process on any one of a soldering material, silicon on glass (SOG), and silica slurry to form the etching mask pattern. 
     
     
         5 . The method of  claim 1 , wherein performing the etch-back process uses a selective wet etchant including HNO 3 , HF, CH 3 COOH, and H 2 O in a volume ratio of 10:0.1-0.01:1-3:5-10. 
     
     
         6 . The method of  claim 5 , wherein the first emitter layer of the selective emitter layer is etched at an etching speed of 0.08 to 0.12 μm/sec using the selective wet etchant, and the second emitter layer of the selective emitter layer is etched at an etching speed of 0.01 to 0.03 μm/sec using the selective wet etchant. 
     
     
         7 . The method of  claim 1 , wherein performing the etch-back process uses an alkali wet etchant or a plasma dry etchant. 
     
     
         8 . The method of  claim 1 , wherein after performing the etch-back process on the emitter layer, a surface resistance of the first emitter layer is within the range of 50 Ohm/sq to 120 Ohm/sq. 
     
     
         9 . The method of  claim 1 , wherein after performing the etch-back process on the emitter layer, a surface resistance of the second emitter layer is within the range of 100 Ohm/sq to 120 Ohm/sq. 
     
     
         10 . The method of  claim 1 , wherein a surface resistance of the first emitter layer is less than a surface resistance of the second emitter layer. 
     
     
         11 . The method of  claim 1 , wherein the etching mask pattern has a lattice shape. 
     
     
         12 . The method of  claim 11 , wherein an interval between the etching mask patterns is within the range of 1 to 3 mm. 
     
     
         13 . The method of  claim 11 , wherein a width of the etching mask pattern is within the range of 50 to 200 μm. 
     
     
         14 . The method of  claim 1 , wherein a width of the first emitter layer is formed wider than a width of the upper electrode. 
     
     
         15 . The method of  claim 1 , wherein the plurality of upper electrodes is positioned only on the first emitter layer along extending a first direction. 
     
     
         16 . The method of  claim 1 , wherein the first emitter layer comprises a plurality of first portions extending in the first direction parallel to the plurality of upper electrodes and a plurality of second portions extending in a second direction crossing the first direction.