Resist hardening and development processes for semiconductor device manufacturing

Abstract

In some embodiments, a method of forming an etch mask on a substrate is provided that includes (1) forming a resist layer on a substrate; (2) exposing one or more regions of the resist layer to an energy source so as to alter at least one of a physical property and a chemical property of the exposed regions; (3) performing a hardening process on the resist layer to increase the etch resistance of first regions of the resist layer relative to second regions of the resist layer, the hardening process including exposing the resist layer to one or more reactive species within an atomic layer deposition (ALD) chamber; and (4) dry etching the resist layer to remove the one or more second regions and to form a pattern in the resist layer. Other embodiments are provided.

The invention claimed is: 
     
         1 . A processing system configured to process a substrate comprising:
 an atomic layer deposition chamber (ALD) configured to perform a hardening process on a substrate having a resist layer formed on the substrate with one or more exposed regions of the resist layer at least one of physically and chemically altered by exposure to at least one of ultra-violet light, extreme-ultra-violet light and an electron beam, the hardening process increasing the etch resistance of first regions of the resist layer relative to second regions of the resist layer;   an etch chamber configured to receive the substrate from the ALD chamber and to etch the resist layer to remove the one or more second regions and to form a pattern in the resist layer; and   a controller configured to control operation of the processing system to:
 transfer the substrate into the ALD chamber; 
 perform the hardening process on the resist layer in the ALD chamber by exposing the resist layer to one or more reactive species within the ALD chamber; 
 transfer the substrate to the etch chamber; and 
 etch the resist layer within the etch chamber to remove the one or more second regions of the resist layer.