System and method for fabricating high voltage power mosfet

Abstract

A high voltage power MOSFET includes a semiconductor substrate doped by a first conducting type, a source doped by a second conducting type and over the semiconductor substrate, and a drain region doped by the second conducting type and on the semiconductor substrate. One or more drain layers doped by the second conducting type and on the semiconductor substrate span between the body region and the drain region. An insulating layer is formed on at least a portion of the body region and over the one or more drain layers. A voltage regulating layer on the insulating layer can produce voltage distributions in the one or more drain layers to deplete charge carriers to increase blockage voltage in an off state, and to accumulate charge carriers in an on state to reduce on-state resistance.

What is claimed is: 
     
         1 . A high voltage power MOSFET, comprising:
 a semiconductor substrate doped by a first conducting type;   a source doped by a second conducting type and over the semiconductor substrate;   a drain region doped by the second conducting type and on the semiconductor substrate;   one or more drain layers doped by the second conducting type and on the semiconductor substrate, wherein the one or more drain layers span between the body region and the drain region;   a body region doped by the first conducting type and configured to separate the source from the one or more drain layers and the drain region;   an insulating layer formed on at least a portion of the body region and over the one or more drain layers;   a voltage regulating layer on the insulating layer, wherein the voltage regulating layer includes a first end electrically connected with the source and a second end electrically connected with the drain region; and   a gate on the insulating layer and at least in part over the source.   
     
     
         2 . The high voltage power MOSFET of  claim 1 , wherein the insulating layer is formed on and covers the section of the body region that is sandwiched between the source and the one or more drain layers. 
     
     
         3 . The high voltage power MOSFET of  claim 1 , wherein the voltage regulating layer includes a resistive layer. 
     
     
         4 . The high voltage power MOSFET of  claim 3 , wherein cross-sectionally the resistive layer includes a continuous portion between the first end and the second end. 
     
     
         5 . The high voltage power MOSFET of  claim 1 , wherein the first voltage regulating layer includes a layer of serially connected P-N junctions. 
     
     
         6 . The high voltage power MOSFET of  claim 5 , wherein the layer of serially connected P-N junctions includes multiple pairs of P-N junctions connected back-to-back. 
     
     
         7 . The high voltage power MOSFET of  claim 5 , wherein the layer of serially connected P-N junctions includes multiple serially connected uni-directional P-N junctions. 
     
     
         8 . The high voltage power MOSFET of  claim 1 , wherein the voltage regulating layer includes a first layer of serially connected P-N junctions,
 the high voltage power MOSFET further comprising:   one or more second layers of serially connected P-N junctions connected in parallel to the first layer of serially connected P-N junctions.   
     
     
         9 . The high voltage power MOSFET of  claim 1 , wherein the voltage regulating layer includes at least two serially connected P-N junctions that are connected in parallel with each other within the voltage regulating layer. 
     
     
         10 . A high voltage power MOSFET, comprising:
 a semiconductor substrate doped by a first conducting type;   a source doped by a second conducting type and over the semiconductor substrate;   a drain region doped by the second conducting type and on the semiconductor substrate;   one or more drain layers doped by the second conducting type and on the semiconductor substrate, wherein the one or more drain layers span between the body region and the drain region;   a body region doped by the first conducting type and configured to separate the source from the one or more drain layers and the drain region;   an insulating layer formed on at least a portion of the body region and over the one or more drain layers;   a voltage regulating layer on the insulating layer including a layer of serially connected P-N junctions comprising multiple serially connected uni-directional P-N junctions; and   a gate on the insulating layer and at least in part over the source.   
     
     
         11 . The high voltage power MOSFET of  claim 10 , wherein the voltage regulating layer includes at least two serially connected P-N junctions that are connected in parallel with each other within the voltage regulating layer. 
     
     
         12 . The high voltage power MOSFET of  claim 10 , wherein the voltage regulating layer includes a first end electrically connected with the source and a second end electrically connected with the drain region. 
     
     
         13 . The high voltage power MOSFET of  claim 10 , wherein the layer of serially connected P-N junctions includes a first end electrically connected with the gate and a second end electrically connected to the drain region. 
     
     
         14 . The high voltage power MOSFET of  claim 10 , wherein the voltage regulating layer is configured to accumulate charge carriers in an on state to reduce on-state resistance. 
     
     
         15 . A high voltage power MOSFET, comprising:
 a semiconductor substrate doped by a first conducting type;   a source doped by a second conducting type and over the semiconductor substrate;   a drain region doped by the second conducting type and on the semiconductor substrate;   one or more drain layers doped by the second conducting type and on the semiconductor substrate, wherein the one or more drain layers span between the body region and the drain region;   a body region doped by the first conducting type and configured to separate the source from the one or more drain layers and the drain region;   an insulating layer formed on at least a portion of the body region and over the one or more drain layers;   a first voltage regulating layer on the insulating layer;   a second voltage regulating layer over the first voltage regulating layer; and   a gate on the insulating layer and at least in part over the source,   
     
     
         16 . The high voltage power MOSFET of  claim 15 , wherein at least one of the first voltage regulating layer and the second voltage regulating layer includes a layer of serially connected P-N junctions. 
     
     
         17 . The high voltage power MOSFET of  claim 16 , wherein the first voltage regulating layer includes a first layer of serially connected P-N junctions, and wherein the second voltage regulating layer includes a layer of serially connected P-N junctions. 
     
     
         18 . The high voltage power MOSFET of  claim 15 , wherein at least one of the first voltage regulating layer and the second voltage regulating layer comprises multiple serially connected uni-directional P-N junctions. 
     
     
         19 . The high voltage power MOSFET of  claim 15 , wherein at least one of the first voltage regulating layer and the second voltage regulating layer comprises multiple pairs of P-N junctions connected back-to-back. 
     
     
         20 . The high voltage power MOSFET of  claim 15 , wherein the first voltage regulating layer includes a first end electrically connected with the gate and a second end electrically connected with the drain region. 
     
     
         21 . The high voltage power MOSFET of  claim 15 , wherein the first voltage regulating layer and the second voltage regulating layer are configured to accumulate charge carriers in an on state to reduce on-state resistance.