System, Method and Apparatus for a Scalable Parallel Processor

Abstract

A system and method of parallel processing includes a computer system including a first processor, the first processor being a control flow type processor, a second processor, the second processor being a data flow type processor. The second processor is coupled to a second memory system, the second memory system including instructions stored therein in an order of execution and corresponding events data stored therein in the order of execution. A first one of the instructions are stored at a predefined location in the second memory system. The system also includes a run time events insertion and control unit coupled to the first processor and the second processor. The first processor, the second processor and the run time events insertion and control unit are on a common integrated circuit.

What is claimed is: 
     
         1 . A method of testing a design comprising:
 compiling a test bench application in a first compiler;   loading the compiled test bench application in a test bench memory system coupled to a test bench processor, wherein the test bench processor is a control flow type processor;   simulating a design in a circuit simulator application;   compiling the simulated design in a second compiler;   loading the compiled design application in a design memory system coupled to a design processor, wherein the design processor is a data type processor and wherein the design processor is coupled to the test bench processor by a runtime events insertion and control unit and wherein loading the compiled design application in the design memory system includes a storing a plurality of instructions and storing a corresponding plurality of events data stored therein, wherein the a first one of the plurality of instructions is stored at a predefined location in the design memory system; and   executing a first instruction in the design processor according to an output of a corresponding first instruction in the test bench processor.   
     
     
         2 . The method of  claim 1 , further comprising, comparing an output result from the executed first instruction in the design processor with a current data value. 
     
     
         3 . The method of  claim 2 , further comprising, loading a next instruction when the output result from the executed first instruction in the design processor is the same as the current data value. 
     
     
         4 . The method of  claim 3 , wherein loading the next instruction includes:
 loading a subsequent instruction into a control memory cache; and   simultaneously loading a corresponding subsequent event data into an events data cache.   
     
     
         5 . The method of  claim 2 , further comprising, storing the output result when the output result from the executed first instruction in the design processor is different than the current data value. 
     
     
         6 . The method of  claim 5 , wherein storing the output result includes storing the output result in an operations cache memory and loading a next instruction in the design processor. 
     
     
         7 . The method of  claim 1 , wherein the first compiler is a functional equivalent of the second compiler. 
     
     
         8 . The method of  claim 1 , wherein the first compiler and the second compiler are C compilers. 
     
     
         9 . The method of  claim 1 , wherein compiling the simulated design in a second compiler includes compiling the simulated design in a MISA compiler followed by compiling the MISA compiled design in the second compiler.