Limited range vector memory access instructions, processors, methods, and systems

Abstract

A processor of an aspect includes a plurality of packed data registers. The processor also includes a unit coupled with the packed data registers. The unit is operable, in response to a limited range vector memory access instruction. The instruction is to indicate a source packed memory indices, which is to have a plurality of packed memory indices, which are to be selected from 8-bit memory indices and 16-bit memory indices. The unit is operable to access memory locations, in only a limited range of a memory, in response to the limited range vector memory access instruction. Other processors are disclosed, as are methods, systems, and instructions.

1 .- 20 . (canceled) 
     
     
         21 . A processor comprising:
 a plurality of packed data registers;   a decode unit to decode an instruction that is to indicate a source packed data register of the plurality of packed data registers that is to have at least eight packed memory indices, which are each to have no more than 16-bits, and the instruction to indicate a destination packed data register of the plurality of packed data registers; and   an execution unit coupled with the decode unit and coupled with the packed data registers, the execution unit, in response to the instruction, to load an entire range of memory that is capable of being uniquely indexed by each of the memory indices with less load operations than a number of the at least eight packed memory indices, and wherein the processor is to access a memory having the range of memory with at least one memory address of at least 32-bits.   
     
     
         22 . The processor of  claim 21 , wherein the execution unit, in response to the instruction, is to selectively move a subset of data elements of the loaded entire range of memory to the destination packed data register based on the memory indices. 
     
     
         23 . The processor of  claim 21 , wherein the execution unit, in response to the instruction, is to load the entire range of memory that is to comprise only 256 different uniquely indexable storage locations. 
     
     
         24 . The processor of  claim 21 , wherein the decode unit is to decode the instruction that is to indicate the source packed data register that is to have the at least eight packed memory indices that are each to have only 8-bits. 
     
     
         25 . The processor of  claim 21 , wherein the decode unit is to decode the instruction that is to indicate the source packed data register that is to have the at least eight packed memory indices that are each to have only 16-bits. 
     
     
         26 . The processor of  claim 21 , wherein the processor, in response to the instruction, is to access the memory having the range of memory with at least one memory address of at least 64-bits. 
     
     
         27 . The processor of  claim 21 , wherein the decode unit is to decode the instruction that is to indicate the source packed data register that is to have at least thirty-two packed memory indices. 
     
     
         28 . A processor comprising:
 a plurality of packed data registers each having at least 128-bits;   a decode unit to decode an instruction that is to indicate a source packed data register of the plurality of packed data registers that is to have a plurality of packed memory indices, which are each to have one of only 8-bits and only 16-bits, and the instruction to indicate a destination packed data register of the plurality of packed data registers; and   an execution unit coupled with the decode unit and coupled with the packed data registers, the execution unit, in response to the instruction, to store a packed data result in the destination packed data register, the packed data result to have a plurality of data elements that are each to correspond to a different one of the plurality of packed memory indices, each of the data elements of the packed data result to be from only a limited range of a memory, and at least one of the data elements of the packed data result to have been loaded using a memory address of at least 32-bits that is to have been derived with a corresponding one of the packed memory indices.   
     
     
         29 . The processor of  claim 28 , wherein the decode unit is to decode the instruction that is to indicate the source packed data register that is to have the packed memory indices that are each to have said only 8-bits. 
     
     
         30 . The processor of  claim 28 , wherein the decode unit is to decode the instruction that is to indicate the source packed data register that is to have the packed memory indices that are each to have said only 16-bits. 
     
     
         31 . The processor of  claim 28 , wherein the execution unit, in response to the instruction, is to load at least one of the plurality of data elements using a memory address of at least 64-bits. 
     
     
         32 . The processor of  claim 28 , wherein the limited range of the memory consists of a number of storage locations that is uniquely indexable by each of the memory indices. 
     
     
         33 . The processor of  claim 28 , wherein the decode unit is to decode the instruction that is to indicate the source packed data register that is to have at least thirty-two packed memory indices. 
     
     
         34 . A processor comprising:
 a plurality of packed data registers each having at least 128-bits;   a decode unit to decode an instruction that is to indicate a source packed data register of the plurality of packed data registers that is to have a plurality of packed memory indices, which are each to have one of only 8-bits and only 16-bits, the instruction to indicate a packed data operation mask that is to have a plurality of mask elements that are each to correspond to a different one of the plurality of packed memory indices, and the instruction to indicate a destination packed data register of the plurality of packed data registers; and   an execution unit coupled with the decode unit and coupled with the packed data registers, the execution unit, in response to the instruction, to store a packed data result in the destination packed data register, the packed data result to have a plurality of data elements that are each to correspond to a different one of the plurality of mask elements of the packed data operation mask, each data element of the packed data result that does not correspond to a masked out mask element of the packed data operation mask to be from only a limited range of a memory, at least one of the data elements of the packed data result to have been loaded using a memory address of at least 32-bits that is to have been derived with a corresponding one of the packed memory indices.   
     
     
         35 . The processor of  claim 34 , wherein the execution unit, in response to the instruction, is to load at least one of the plurality of data elements using a memory address of at least 64-bits. 
     
     
         36 . The processor of  claim 34 , wherein the decode unit is to decode the instruction that is to indicate the source packed data register that is to have at least thirty two packed memory indices.