US2016372672A1PendingUtilityA1

Semiconductor device

66
Assignee: SEMICONDUCTOR ENERGY LABPriority: Feb 12, 2003Filed: Aug 29, 2016Published: Dec 22, 2016
Est. expiryFeb 12, 2023(expired)· nominal 20-yr term from priority
G02F 1/13306G02F 1/13439G02F 1/1368G02F 1/13454G02F 1/13452G02F 1/134309G02F 1/1339G02F 2202/28G02F 1/1341H10P 72/7434H10W 10/181H10P 72/0478H10P 72/0468H10P 72/0464H10P 72/74H10W 90/291H10W 90/20H10W 72/9226H10W 72/07251H10W 72/942H10W 72/923H10W 72/823H10W 72/244H10W 72/20H10W 90/00H10W 90/722H10P 90/1914H10K 71/50H10D 86/441H10D 86/421H10D 86/0223H10D 86/0214H10D 86/60H10D 86/40H10D 30/6745H10D 30/6731H10H 29/10H01L 51/5092H01L 21/67236H01L 25/50H01L 51/5088H01L 27/124H01L 27/3248H01L 27/1266H01L 27/1222H01L 51/0024H01L 51/56H01L 27/3276H01L 51/5056H01L 51/5072H01L 21/67196H01L 51/003H01L 25/0657H01L 51/5096H01L 51/5012H01L 27/1274H01L 51/5206H01L 51/5221H01L 27/3272H01L 29/78675H01L 21/67207G02F 1/13456H10K 59/131H10K 50/15H10K 50/171H10K 2102/103H10K 59/1201H10K 50/16H10K 71/80H10K 59/123H10K 2102/3031H10K 59/126H10K 50/11
66
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

The present invention intends to realize a narrow frame of a system on panel. In addition to this, a system mounted on a panel is intended to make higher and more versatile in the functionality. In the invention, on a panel on which a pixel portion (including a liquid crystal element, a light-emitting element) and a driving circuit are formed, integrated circuits that have so far constituted an external circuit are laminated and formed. Specifically, of the pixel portion and the driving circuit on the panel, on a position that overlaps with the driving circuit, any one kind or a plurality of kinds of the integrated circuits is formed by laminating according to a transcription technique.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device comprising:
 a substrate;   a pixel portion over the substrate, wherein the pixel portion comprise a light emitting element;   a source driving circuit over the substrate; and   a layered circuit over the source driving circuit, the layered circuit comprising:
 a first integrated circuit; and 
 a second integrated circuit over the first integrated circuit; 
   wherein the source driving circuit and the layered circuit are electrically connected via a bump.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.