US2017011913A1PendingUtilityA1
Method for fabricating a semiconductor structure
Est. expiryAug 27, 2034(~8.1 yrs left)· nominal 20-yr term from priority
H10P 50/646H10P 14/3432H10P 14/3431H10P 14/3428H10P 14/3421H10P 14/3418H10P 14/3414H10P 14/3402H10P 14/3256H10P 14/3238H10P 14/3214H10P 14/2913H10P 14/2907H10P 14/2905H10P 14/272H10P 14/271H10P 14/38H10P 14/24H10P 14/276H10D 86/423H10D 86/411H10D 86/60H10D 84/08H10D 62/115H10D 62/86H10D 62/85H10D 62/83H10D 62/53H10D 30/6758H10D 30/6757H10D 30/675H01L 21/02557H01L 29/20H01L 21/02562H01L 21/02488H01L 21/0262H01L 21/02381H01L 21/0256H01L 29/0649H01L 29/78696H01L 21/02513H01L 21/02546H01L 21/02543H01L 29/32H01L 29/22H01L 29/78681
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Claims
Abstract
Method for fabricating a semiconductor structure. The semiconductor structure includes: a crystalline silicon substrate; a dielectric layer on the crystalline silicon substrate, the opening having an opening with sidewalls and a bottom wherein the bottom corresponds to a surface of the crystalline silicon substrate; and a crystalline compound semiconductor layer thereby forming a processable crystalline compound semiconductor substrate, wherein the bottom of the opening is isolated from the crystalline compound material.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A semiconductor structure comprising:
a crystalline silicon material substrate; a dielectric layer on the crystalline silicon substrate having an opening with sidewalls and a bottom wherein the bottom corresponds to a surface of the crystalline silicon substrate; and a crystalline compound semiconductor layer at least partially covering the dielectric layer thereby forming a processable crystalline compound semiconductor substrate, wherein the bottom of the opening is isolated from the crystalline compound material.
2 . The semiconductor structure of claim 1 , wherein a surface of the crystalline semiconductor compound layer has a surface structure corresponding to: (i) a surface structure of a sacrificial layer used for supporting a confinement structure during manufacture of the semiconductor structure, or (ii) a surface structure of a cap layer of a confinement structure used during growth of the crystalline semiconductor compound layer.
3 . A wafer structure comprising a plurality of semiconductor structures or devices of claim 1 .Join the waitlist — get patent alerts
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