Memory buffering system that improves read/write performance and provides low latency for mobile systems

Abstract

A memory buffering system is disclosed that arbitrates bus ownership through an arbitration scheme for memory elements in chain architecture. A unified host memory controller arbitrates bus ownership for transfer to a unified memory buffer and other buffers within the chain architecture. The system is used within a communication system with a bus in chain architectures and parallel architectures.

What is claimed is: 
     
         1 . A memory buffering system comprising:
 a transfer bus;   a unified memory controller (UMC) comprising a unified host buffer and a request queue; and   a plurality of clients coupled together in a chain architecture, each of the plurality of clients comprising a respective memory element and a corresponding buffer, the plurality of clients being configured to communicate with the unified host buffer in a series bus configuration;   wherein the UMC is configured to allocate available buffer space of the corresponding buffer of each of the plurality of clients situated upstream from a memory element of a client being accessed from among the plurality of clients.