Method for processing a carrier, a carrier, and a split gate field effect transistor structure

Abstract

According to various embodiments, a method for processing a carrier may include: doping a carrier with fluorine such that a first surface region of the carrier is fluorine doped and a second surface region of the carrier is at least one of free from the fluorine doping or less fluorine doped than the first surface region; and oxidizing the carrier to grow a first gate oxide layer from the first surface region of the carrier with a first thickness and simultaneously from the second surface region of the carrier with a second thickness different from the first thickness.

What is claimed is: 
     
         1 . A split gate field effect transistor structure comprising:
 a channel comprising a first body region and a second body region,   a first split gate isolation layer structure disposed over a first body region of the channel and having a first thickness,   a second split gate isolation layer structure disposed over a second body region of the channel and having a second thickness, wherein the second thickness is less than the first thickness;   a gate comprising a first gate portion disposed over the first split gate isolation layer structure and a second gate portion disposed over the second split gate isolation layer structure;   wherein an electrical conductivity of the second gate portion is greater than the electrical conductivity of the first gate portion.   
     
     
         2 . The split gate field effect transistor structure of  claim 1 ,
 wherein the first gate portion comprises a semiconductor material with a first doping concentration and wherein the second gate portion comprises a semiconductor material with a second doping concentration, wherein the second doping concentration is greater than the first doping concentration.   
     
     
         3 . The carrier of  claim 2 ,
 wherein the second doping concentration is about 1*10 21  cm −3 .   
     
     
         4 . The split gate field effect transistor structure of  claim 1 ,
 wherein the first split gate isolation layer structure comprises a double layer gate isolation.   
     
     
         5 . The split gate field effect transistor structure of  claim 4 ,
 wherein the double layer gate isolation is provided with the first thickness in the range from about 4 nm to about 10 nm.   
     
     
         6 . The split gate field effect transistor structure of  claim 1 ,
 wherein the second split gate isolation layer structure comprises a single layer gate isolation.   
     
     
         7 . The split gate field effect transistor structure of  claim 6 ,
 wherein the single layer gate isolation is provided with the second thickness in the range from about 1 nm to about 3 nm.   
     
     
         8 . The split gate field effect transistor structure of  claim 1 ,
 wherein the ratio of the first thickness to the second thickness is greater than about 2.   
     
     
         9 . The split gate field effect transistor structure of  claim 1 ,
 wherein the split gate field effect transistor structure is configured as one-time programmable fuse, wherein the second split gate region provides the programming area.   
     
     
         10 . A carrier comprising:
 a first carrier region, a second carrier region, and a third carrier region respectively next to each other;   a first field effect transistor in the first carrier region, the first field effect transistor comprising a first single layer gate isolation having a first thickness;   a second field effect transistor in the second carrier region, the second field effect transistor comprising a first double layer gate isolation having a second thickness; and   a split gate field effect transistor structure in the third carrier region; the split gate field effect transistor structure comprising:   a channel comprising a first body region and a second body region,   a first split gate isolation layer structure disposed over a first body region of the channel and having a third thickness,   a second split gate isolation layer structure disposed over a second body region of the channel and having a fourth thickness, wherein the fourth thickness is less than the third thickness;   a gate comprising a first gate portion disposed over the first split gate isolation layer structure and a second gate portion disposed over the second split gate isolation layer structure;   wherein an electrical conductivity of the second gate portion is greater than the electrical conductivity of the first gate portion.   
     
     
         11 . The carrier of  claim 10 ,
 wherein the first split gate isolation layer structure comprises a double layer gate isolation.   
     
     
         12 . The carrier of  claim 11 ,
 wherein the double layer gate isolation is provided with the third thickness in the range from about 4 nm to about 10 nm.   
     
     
         13 . The carrier of  claim 10 ,
 wherein the second split gate isolation layer structure comprises a single layer gate isolation.   
     
     
         14 . The carrier of  claim 13 ,
 wherein the single layer gate isolation is provided with the fourth thickness in the range from about 1 nm to about 3 nm.   
     
     
         15 . The carrier of  claim 10 ,
 wherein the first thickness of the first single layer gate isolation is less than about 3.5 nm.   
     
     
         16 . The carrier of  claim 10 ,
 wherein the second thickness of the first double layer gate isolation is greater than about 3.5 nm.   
     
     
         17 . The carrier of  claim 10 ,
 wherein the carrier is at least one of p-type doped with acceptors from Group III elements or n-type doped with donors from Group V elements.   
     
     
         18 . The carrier of  claim 10 ,
 wherein the third carrier region is fluorine doped.   
     
     
         19 . The carrier of  claim 16 ,
 wherein the first carrier region and the second carrier region are at least one of free from the fluorine doping or less fluorine doped than the third surface region.   
     
     
         20 . The carrier of  claim 10 ,
 wherein the split gate field effect transistor structure is configured as a one-time programmable device, wherein the second split gate region provides the programming area.