Method of Manufacturing an Integrated Circuit

Abstract

A method of manufacturing an integrated circuit includes: growing an epitaxial layer on a process surface of a base substrate; forming, by processes applied to an exposed first surface of the epitaxial layer, first transistor cells in the epitaxial layer, each first transistor cell including a first gate electrode; and forming, by processes applied to a surface opposite to the first surface, second transistor cells, each second transistor cell including a second gate electrode.

What is claimed is: 
     
         1 . A method of manufacturing an integrated circuit, the method comprising:
 growing an epitaxial layer on a process surface of a base substrate;   forming, by processes applied to an exposed first surface of the epitaxial layer, first transistor cells in the epitaxial layer, each first transistor cell comprising a first gate electrode; and   forming, by processes applied to a surface opposite to the first surface, second transistor cells, each second transistor cell comprising a second gate electrode.   
     
     
         2 . The method of  claim 1 , further comprising:
 removing at least a portion of the base substrate after forming the first transistor cells and before forming the second transistor cells.   
     
     
         3 . The method of  claim 1 , wherein the second transistor cells are formed in the epitaxial layer. 
     
     
         4 . The method of  claim 1 , wherein the second transistor cells are formed in the base substrate. 
     
     
         5 . The method of  claim 1 , further comprising:
 growing, after forming the first transistor cells, a further epitaxial layer on a side of the base substrate opposite to the epitaxial layer with the first transistor cells, wherein the second transistor cells are formed in the further epitaxial layer.   
     
     
         6 . The method of  claim 1 , further comprising:
 forming, before growing the epitaxial layer, an auxiliary structure from a material different from a material of the base substrate on the process surface.   
     
     
         7 . The method of  claim 6 , further comprising:
 removing, before forming the second transistor cells, the base substrate after forming the first transistor cells, wherein the auxiliary structure and a second surface are exposed.   
     
     
         8 . The method of  claim 7 , wherein forming the second transistor cells comprises forming the second gate electrodes of the second transistor cells on the second surface. 
     
     
         9 . The method of  claim 8 , further comprising:
 removing, before forming the second transistor cells, the auxiliary structure selectively against the epitaxial layer so as to form a device connection groove.   
     
     
         10 . The method of  claim 9 , further comprising:
 forming a device connection structure in the device connection groove.   
     
     
         11 . The method of  claim 10 , wherein the first transistor cells are vertical transistor cells, forming the first transistor cells comprises forming a common drain zone of the first transistor cells in the epitaxial layer, and wherein the device connection structure directly adjoins the common drain zone. 
     
     
         12 . The method of  claim 6 , wherein the auxiliary structure is formed from a dielectric material. 
     
     
         13 . The method of  claim 1 , wherein forming the epitaxial layer comprises forming at least two group III nitride layers. 
     
     
         14 . The method of  claim 13 , wherein forming the first transistor cells comprises forming a first source contact and a first drain contact extending from a first surface of the epitaxial layer into the epitaxial layer, wherein one of the first source contact and the first drain contact extends into the base substrate. 
     
     
         15 . The method of  claim 14 , wherein forming the first transistor cells further comprises forming a first gate electrode on the first surface of the epitaxial layer. 
     
     
         16 . The method of  claim 14 , further comprising:
 growing, after forming the first transistor cells, a further epitaxial layer on a side of the base substrate opposite to the epitaxial layer with the first transistor cells, wherein the second transistor cells are formed in the further epitaxial layer.   
     
     
         17 . The method of  claim 16 , wherein forming the second transistor cells comprises forming a second source contact and a second drain contact extending from a second surface of the further epitaxial layer into the epitaxial layer, wherein one of the second drain contact and the second source contact extends into the base substrate. 
     
     
         18 . The method of  claim 17 , wherein the base substrate is conductive. 
     
     
         19 . The method of  claim 17 , wherein either the first drain contact and the second source contact or the second drain contact and the first source contact directly adjoin to each other and form a continuous device connection structure extending from the first surface to the second surface.