Semiconductor device, electronic component, and electronic device

Abstract

To provide a semiconductor device having a novel structure. To provide a semiconductor device excellent in reducing power consumption. A memory cell including an SRAM capable of backing up data to the nonvolatile memory and a peripheral circuit of the memory cell are configured to offer different power gating states. In a first period, which is extremely short, the bit line is brought into an electrically floating state by turning off the switch. In a second period, which is longer than the first period, power gating is performed on the memory cell. In a third period, which is longer than the second period, power gating is performed on the memory cell and the peripheral circuits.

1 . (canceled) 
     
     
         2 . A semiconductor device comprising:
 a control circuit;   a memory circuit electrically connected to a bit line; and   a peripheral circuit,   wherein the control circuit is configured to switch three different states,   wherein in the first state, the bit line is brought into an electrically floating state,   wherein in the second state, a supply of a power supply voltage to the memory circuit is stopped, and   wherein in the third state, the supply of the power supply voltage to the memory circuit and a supply of a power supply voltage to the peripheral circuit are stopped.   
     
     
         3 . The semiconductor device according to  claim 2 ,
 wherein the memory circuit comprises an SRAM.   
     
     
         4 . The semiconductor device according to  claim 3 ,
 wherein the memory circuit further comprises a first transistor and a capacitor, and   wherein the first transistor comprises an oxide semiconductor in a semiconductor layer.   
     
     
         5 . The semiconductor device according to  claim 4 ,
 wherein the SRAM comprises a second transistor, and   wherein the second transistor includes silicon in a semiconductor layer.   
     
     
         6 . The semiconductor device according to  claim 5 ,
 wherein a channel region of the first transistor and a channel region of the second transistor overlap with each other.   
     
     
         7 . The semiconductor device according to  claim 2 ,
 wherein in the first state, a period during which there is no access to the memory circuit is longer than a first period,   wherein in the second state, a period during which there is no access to the memory circuit is longer than a second period,   wherein in the third state, a period during which there is no access to the memory circuit is longer than a third period,   wherein the third period is longer than the second period, and   wherein the second period is longer than the first period.   
     
     
         8 . A semiconductor device comprising:
 a control circuit;   a memory circuit electrically connected to a bit line; and   a peripheral circuit,   wherein the control circuit is configured to switch three different states,   wherein in the first state, the bit line is brought into an electrically floating state, and   wherein in the second state, a supply of a power supply voltage to the memory circuit and the peripheral circuit is stopped.   
     
     
         9 . The semiconductor device according to  claim 8 ,
 wherein the memory circuit comprises an SRAM.   
     
     
         10 . The semiconductor device according to  claim 9 ,
 wherein the memory circuit further comprises a first transistor and a capacitor, and   wherein the first transistor comprises an oxide semiconductor in a semiconductor layer.   
     
     
         11 . The semiconductor device according to  claim 10 ,
 wherein the SRAM comprises a second transistor, and   wherein the second transistor includes silicon in a semiconductor layer.   
     
     
         12 . The semiconductor device according to  claim 11 ,
 wherein a channel region of the first transistor and a channel region of the second transistor overlap with each other.   
     
     
         13 . The semiconductor device according to  claim 8 ,
 wherein in the first state, a period during which there is no access to the memory circuit is longer than a first period,   wherein in the second state, a period during which there is no access to the memory circuit is longer than a second period, and   wherein the second period is longer than the first period.