US2017062425A1PendingUtilityA1

Semiconductor Device Having Features to Prevent Reverse Engineering

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Assignee: VERISITI INCPriority: Jun 7, 2011Filed: Mar 8, 2016Published: Mar 2, 2017
Est. expiryJun 7, 2031(~4.9 yrs left)· nominal 20-yr term from priority
H10W 42/40H03K 19/20H01L 23/573H01L 27/0922H10D 1/474H10D 89/00H10D 84/01H10D 84/00H10D 84/856
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Claims

Abstract

It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An electronic element comprising:
 a first device having a first geometry and a first characteristic;   a second device having a second geometry and a second characteristic, wherein the first geometry and the second geometry are the same and the second characteristic is different than the first characteristic; and   an output, wherein a level of the output is dependent upon a difference in the first characteristic and the second characteristic, wherein the difference is determined by a difference in doping levels of the first device and the second device.

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