Adaptively strengthening ecc for solid state cache

Abstract

In an aspect of the subject matter, a “full” amount of the flash cache (e.g., storage cells) is initially utilized to store data i.e., substantially all of the storage space of the flash cache may be designated to store user data, with the remaining storage space designated to store ECC information (e.g., parity bits) associated with a predefined ECC algorithm utilized to encode the user data. When a bit errors associated with the user data reaches a predefined threshold value, the storage space of the flash cache may transition to store less user data so as to accommodate the space needed to store ECC information associated with a stronger ECC algorithm. The storage space of the flash cache designated to store user data is reduced, while the storage space designated to store ECC information is increased to accommodate the stronger ECC algorithm.

1 . A non-transitory machine readable medium having stored thereon instructions for performing a method comprising machine executable code which when executed by at least one machine, causes the machine to:
 apportion a solid state device having storage space into two sections, a first section of the storage space configured to store user data and a second section of the storage space configured to store redundancy information for the user data;   determine a bit error rate associated with user data stored on the solid state device; and   increase the storage space of the second section configured to store the redundancy information and decrease the storage space of the first section configured to store the user data, when the determined bit error rate associated with the user data has reached a predefined threshold.   
     
     
         2 . The non-transitory machine readable medium as set forth in  claim 1 , wherein the machine executable code when executed by the machine further causes the machine to increase the second section by a first amount and decrease the first section by the first amount. 
     
     
         3 . The non-transitory machine readable medium as set forth in  claim 1 , wherein the redundancy information, stored in the second section prior to increasing the storage space of the second section, is associated with a first error correction code algorithm. 
     
     
         4 . The non-transitory machine readable medium as set forth in  claim 3 , wherein the redundancy information, stored in the second section after increasing the storage space of the second section, is associated with a second error correction code algorithm that is stronger than the first error correction algorithm. 
     
     
         5 . The non-transitory machine readable medium as set forth in  claim 1 , wherein the machine executable code when executed by the machine further causes the machine to increase the storage space of the second section by a further amount and decrease the storage space of the second section by the further amount, when the determined bit error rate associated with the user data has increased and reached a different predefined threshold. 
     
     
         6 . The non-transitory machine readable medium as set forth in  claim 1 , wherein the solid state device is a multi-level cell (MLC) NAND solid state cache. 
     
     
         7 . The non-transitory machine readable medium as set forth in  claim 6 , wherein the first section and second section together define a page of the MLC NAND solid state cache. 
     
     
         8 . The non-transitory machine readable medium as set forth in  claim 1 , wherein the machine executable code when executed by the machine further causes the machine to allocate a third section of storage space of the solid state device to store the redundancy data, when the determined bit error rate associated with the user data has increased and reached a different predefined threshold, wherein the first section and the second section together define a first page of the solid state device and the third section is part of a different page of the solid state device. 
     
     
         9 . A method comprising:
 apportioning, by a computing device, a solid state device having storage space including cells into two sections, a first section of the storage space configured to store user data and a second section of the storage space configured to store redundancy information for the user data, where each cell of the two sections stores a first number of bits; and   determining, by the computing device, whether a bit error rate associated with user data stored on the solid state device has reached a predefined threshold, and the process further executable to change each cell of the two section to store a second number of bits that is less than the first number of bits, in response to determining that the bit error rate associated with the user data has reached a predefined threshold.   
     
     
         10 . The method of  claim 9 , wherein the redundancy information, is associated with an error correction code algorithm. 
     
     
         11 . The method of  claim 9 , wherein the first number of bits is 2, and wherein the second number of bits is 1. 
     
     
         12 . The method of  claim 9 , wherein the solid state device is a multi-level cell (MLC) NAND solid state cache. 
     
     
         13 . A non-transitory machine readable medium having stored thereon instructions for performing a method comprising machine executable code which when executed by at least one machine, causes the machine to:
 apportion a solid state device having storage space including cells into two sections, a first section of the storage space configured to store user data and a second section of the storage space configured to store redundancy information for the user data, where each cell of the two sections stores a first number of bits;   determine when a bit error rate associated with user data stored on the solid state device has reached a predefined threshold; and   change each cell of the two section to store a second number of bits that is less than the first number of bits, in response to determining that the bit error rate associated with the user data has reached a predefined threshold.   
     
     
         14 . The non-transitory machine readable medium as set forth in  claim 13 , wherein the redundancy information, is associated with an error correction code algorithm. 
     
     
         15 . The non-transitory machine readable medium as set forth in  claim 13 , wherein the first number of bits is 2, and wherein the second number of bits is 1. 
     
     
         16 . The non-transitory machine readable medium as set forth in  claim 13 , wherein the solid state device is a multi-level cell (MLC) NAND solid state cache.