Method and apparatus for preventing unauthorized access to contents of a register under certain conditions when performing a hardware table walk (hwtw)

Abstract

A security apparatus and method are provided for performing a security algorithm that prevents unauthorized access to contents of a physical address (PA) that have been loaded into a storage element of the computer system as a result of performing a prediction algorithm during a hardware table walk that uses a predictor to predict a PA based on a virtual address (VA). When the predictor is enabled, it might be possible for a person with knowledge of the system to configure the predictor to cause contents stored at a PA of a secure portion of the main memory to be loaded into a register in the TLB. In this way, a person who should not have access to contents stored in secure portions of the main memory could indirectly gain unauthorized access to those contents. The apparatus and method prevent such unauthorized access to the contents by masking the contents under certain conditions.

1 - 19 . (canceled) 
     
     
         20 . An apparatus of a computer system for preventing unauthorized access to contents of a physical address (PA) that have been loaded into a storage element of the computer system during performance of a hardware table walk (HWTW), the apparatus comprising:
 a memory controller configured to perform a first translation of a first address into a second address and to perform a second translation of the second address into a third address, the memory controller further configured to assert a first bit when a read transaction directs the memory controller to perform the second translation of the second address into the third address, the memory controller further configured to assert a second bit when a miss results from performance of the read transaction when determining whether a translation lookaside buffer (TLB) indicates the physical address at which a page table is stored;   a predictor module configured to enable a prediction algorithm that predicts a physical address as a function of the second address and a function of a virtual machine identifier, the predictor module configured to disable HWTW control logic in response to the first bit and the second bit; and   a security logic module configured to prevent unauthorized access to the contents of said storage element from a secure portion of memory when the prediction algorithm is currently enabled by the first bit.   
     
     
         21 . The apparatus of  claim 20 , wherein the first translation comprises a stage 1 translation and the first address comprises a physical address. 
     
     
         22 . The apparatus of  claim 21 , wherein the second address comprises an intermediate physical address, the second translation comprises a stage 2 translation, and the third address comprises a physical address. 
     
     
         23 . The apparatus of  claim 20 , wherein the first bit comprises a prediction enable bit and the second bit comprises a class enable bit. 
     
     
         24 . The apparatus of  claim 20 , wherein the security logic module is configured to allow the contents of said storage element from a non-secure portion of memory to be accessed when the prediction algorithm is currently disabled by the first bit. 
     
     
         25 . The apparatus of  claim 24 , wherein the first bit comprises a prediction enable bit and the second bit comprises a class enable bit. 
     
     
         26 . The apparatus of  claim 20 , wherein the memory controller comprises a memory management unit (MMU) of the computer system. 
     
     
         27 . The apparatus of  claim 26 , wherein the security logic module is part of the MMU of the computer system. 
     
     
         28 . The apparatus of  claim 26 , wherein the MMU is part of central processing unit (CPU) of the computer system. 
     
     
         29 . The apparatus of  claim 28 , wherein the CPU is part of a CPU cluster of the computer system. 
     
     
         30 . A computer-implemented method for preventing unauthorized access to contents of a physical address (PA) that have been loaded into a storage element of a computer system during performance of a hardware table walk (HWTW), the method comprising:
 performing with a processor a first translation of a first address into a second address;   performing with a processor a second translation of the second address into a third address;   asserting a first bit with a processor when a read transaction directs a memory controller to perform the second translation of the second address into the third address;   asserting a second bit with a processor when a miss results from performance of the read transaction when determining whether a translation lookaside buffer (TLB) indicates the physical address at which a page table is stored;   performing a prediction algorithm with a processor that predicts a physical address as a function of the second address and a function of a virtual machine identifier,   disabling HWTW control logic in response to the first bit and the second bit; and   blocking unauthorized access to the contents of said storage element from a secure portion of memory when the prediction algorithm is currently enabled by the first bit.   
     
     
         31 . The method of  claim 30 , further comprising allowing access to contents of said storage element from a non-secure portion of memory when the prediction algorithm is currently disabled by the first bit. 
     
     
         32 . The method of  claim 31 , wherein the first bit comprises a prediction enable bit and the second bit comprises a class enable bit. 
     
     
         33 . The method of  claim 30 , wherein the first bit comprises a prediction enable bit and the second bit comprises a class enable bit. 
     
     
         34 . The method of  claim 33 , wherein the second address comprises an intermediate physical address, the second translation comprises a stage 2 translation, and the third address comprises a physical address. 
     
     
         35 . The method of  claim 30 , wherein the memory controller comprises a memory management unit (MMU) of the computer system. 
     
     
         36 . The method of  claim 35 , wherein the MMU is part of central processing unit (CPU) of the computer system. 
     
     
         37 . The method of  claim 36 , wherein the CPU is part of a CPU cluster of the computer system. 
     
     
         38 . The method of  claim 30 , wherein said storage element is a register of the TLB. 
     
     
         39 . The method of  claim 38 , further comprising loading the predicted physical address into the register if the prediction algorithm is currently enabled. 
     
     
         40 . A computer system for preventing unauthorized access to contents of a physical address (PA) that have been loaded into a storage element of the computer system during performance of a hardware table walk (HWTW), the system comprising:
 processor means for performing a first translation of a first address into a second address;   processor means for performing a second translation of the second address into a third address;   processor means for asserting a first bit with a processor when a read transaction directs a memory controller to perform the second translation of the second address into the third address;   processor means for asserting a second bit with a processor when a miss results from performance of the read transaction when determining whether a translation lookaside buffer (TLB) indicates the physical address at which a page table is stored;   processor means for performing a prediction algorithm with a processor that predicts a physical address as a function of the second address and a function of a virtual machine identifier,   means for disabling HWTW control logic in response to the first bit and the second bit; and   means for blocking unauthorized access to the contents of said storage element from a secure portion of memory when the prediction algorithm is currently enabled by the first bit.   
     
     
         41 . The system of  claim 40 , wherein the means for blocking allows access to contents of said storage element from a non-secure portion of memory when the prediction algorithm is currently disabled by the first bit. 
     
     
         42 . The system of  claim 41 , wherein the first bit comprises a prediction enable bit and the second bit comprises a class enable bit. 
     
     
         43 . The system of  claim 40 , wherein the first bit comprises a prediction enable bit and the second bit comprises a class enable bit. 
     
     
         44 . The system of  claim 43 , wherein the second address comprises an intermediate physical address, the second translation comprises a stage 2 translation, and the third address comprises a physical address. 
     
     
         45 - 49 . (canceled) 
     
     
         50 . A computer program product comprising a non-transitory computer usable medium having a computer readable program code embodied therein, said computer readable program code adapted to be executed to implement a method for preventing unauthorized access to contents of a physical address (PA) that have been loaded into a storage element of a computer system during performance of a hardware table walk (HWTW), said method comprising:
 performing with a processor a first translation of a first address into a second address;   performing with a processor a second translation of the second address into a third address;   asserting a first bit with a processor when a read transaction directs a memory controller to perform the second translation of the second address into the third address;   asserting a second bit with a processor when a miss results from performance of the read transaction when determining whether a translation lookaside buffer (TLB) indicates the physical address at which a page table is stored;   performing a prediction algorithm with a processor that predicts a physical address as a function of the second address and a function of a virtual machine identifier,   disabling HWTW control logic in response to the first bit and the second bit; and   blocking unauthorized access to the contents of said storage element from a secure portion of memory when the prediction algorithm is currently enabled by the first bit.   
     
     
         51 . The computer program product of  claim 50 , wherein the program code implementing the method further comprises: allowing access to contents of said storage element from a non-secure portion of memory when the prediction algorithm is currently disabled by the first bit. 
     
     
         52 . The computer program product of  claim 51 , wherein the first bit comprises a prediction enable bit and the second bit comprises a class enable bit. 
     
     
         53 . The computer program product of  claim 50 , wherein the first bit comprises a prediction enable bit and the second bit comprises a class enable bit. 
     
     
         54 . The computer program product of  claim 53 , wherein the second address comprises an intermediate physical address, the second translation comprises a stage 2 translation, and the third address comprises a physical address. 
     
     
         55 - 59 . (canceled)