US2017131470A1PendingUtilityA1

Compact and low loss Y-junction for submicron silicon waveguide

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Assignee: CORIANT ADVANCED TECH LLCPriority: Nov 30, 2012Filed: Nov 12, 2015Published: May 11, 2017
Est. expiryNov 30, 2032(~6.4 yrs left)· nominal 20-yr term from priority
G06F 30/394G02B 6/125G02B 6/107G02B 6/1228G02B 6/2808G02B 6/1223G02B 2006/12061G02B 27/0012G02B 2006/1215G06N 3/126G02B 2006/12038G06F 30/23G06F 30/20
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Claims

Abstract

A compact, low-loss and wavelength insensitive Y-junction for submicron silicon waveguides. The design was performed using FDTD and particle swarm optimization (PSO). The device was fabricated in a 248 nm CMOS line. Measured average insertion loss is 0.28±0.02 dB across an 8-inch wafer. The device footprint is less than 1.2 μm×2 μm, orders of magnitude smaller than MMI and directional couplers.

Claims

exact text as granted — not AI-modified
1 - 8 . (canceled) 
     
     
         9 . A 1×2 power splitter for use in submicron silicon waveguides, comprising:
 an input port configured to receive an optical signal having an input power; 
 a pair of output ports configured to provide substantially equal output signals; and 
 a tapered waveguide coupling said input port to said output ports comprising a plurality of widths. 
 
     
     
         10 . The 1×2 power splitter for use in submicron silicon waveguides of  claim 9 , wherein said 1×2 power splitter has a minimum feature size of 200 nm. 
     
     
         11 . The 1×2 power splitter for use in submicron silicon waveguides of  claim 9 , wherein said 1×2 power splitter is configured to be manufactured using a CMOS fabrication process. 
     
     
         12 . The 1×2 power splitter for use in submicron silicon waveguides of  claim 11 , wherein said CMOS fabrication process is a process conducted using a 248 nm scanner. 
     
     
         13 . The 1×2 power splitter for use in submicron silicon waveguides of  claim 11 , wherein said CMOS fabrication process is a process conducted using a 193 nm scanner. 
     
     
         14 . The 1×2 power splitter for use in submicron silicon waveguides of  claim 9 , wherein said plurality of widths are selected to reduce excess loss. 
     
     
         15 . A method for making a 1×2 power splitter for use in submicron silicon waveguides, comprising the steps of:
 configuring an input port to receive an optical signal having an input power; 
 configuring a pair of output ports to provide substantially equal output signals; and 
 coupling said input port and to said output ports using a tapered waveguide comprising a plurality of widths. 
 
     
     
         16 . The method of  claim 15 , wherein said plurality of widths can be defined by a numerical algorithm. 
     
     
         17 . The method of  claim 16 , wherein said numerical algorithm is a particle swarm optimization. 
     
     
         18 . The method of  claim 16 , wherein said numerical algorithm is a genetic algorithm.

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