Monitoring accesses of a thread to multiple memory controllers and selecting a thread processor for the thread based on the monitoring

Abstract

A method of an aspect includes running a plurality of threads on a plurality of thread processors. Memory accesses, of a thread of the plurality that is running on a first thread processor of the plurality, are monitored to both a first memory through a first memory controller and a second memory through a second memory controller. A second thread processor of the plurality is selected for a thread based on the monitoring of the memory accesses of the thread to both the first memory and the second memory. Installation of the thread, for which the second thread processor was selected, is initiated on the second thread processor. Other methods, apparatus, and systems are also disclosed.

What is claimed is: 
     
         1 . An apparatus comprising:
 a plurality of thread processors of a multi-core processor to run a plurality of threads;   a first memory controller coupled with the plurality of thread processors, the first memory controller to couple with and to provide access to a first memory;   a second memory controller coupled with the plurality of thread processors, the second memory controller to couple with and to provide access to a second memory;   a memory controller access monitor unit coupled with a first thread processor of the plurality of thread processors, the memory controller access monitor unit to monitor accesses, by a given thread of the plurality of threads that is to run on the first thread processor, to both the first memory controller and the second memory controller; and   a thread processor selector unit coupled with the memory controller access monitor unit, the thread processor selector unit to select a second thread processor of the plurality of thread processors of the multi-core processor for a thread based on the monitored accesses by the given thread to both the first memory controller and the second memory controller, wherein the second thread processor is coupled with the first memory controller through at least one intervening thread processor and is coupled with the second memory controller through at least one intervening thread processor.   
     
     
         2 . The apparatus of  claim 1 , wherein the thread processor selector unit is to select the second thread processor to improve overall memory access latency from the second thread processor to the first and second memories. 
     
     
         3 . The apparatus of  claim 1 , wherein the thread processor selector unit is to select the second thread processor based on a relative proportion of the monitored accesses to the first and second memory controllers. 
     
     
         4 . The apparatus of  claim 1 , wherein the thread processor selector unit is to select the second thread processor based on a first queuing delay, which is to incorporate a queuing delay of an intervening thread processor, and which is to be associated with memory accesses to the first memory and a second queuing delay associated with memory accesses to the second memory. 
     
     
         5 . The apparatus of  claim 1 , wherein the thread processor selector unit is to select the second thread processor for the given thread for which the memory controller access monitor unit is to monitor the accesses to both the first and second memory controllers, and further comprising a thread migration initiation unit to initiate migration of the given thread from the first thread processor to the second thread processor. 
     
     
         6 . The apparatus of  claim 1 , wherein the thread processor selector unit is to select the second thread processor for a second thread which is to be of a same type as the given thread for which the memory controller access monitor unit is to monitor the accesses to both the first and second memory controllers, and further comprising a thread scheduling initiation unit to initiate scheduling of the second thread on the second thread processor. 
     
     
         7 . The apparatus of  claim 1 , further comprising a memory controller access intensity determination unit coupled with the memory controller access monitor unit, the memory controller access intensity determination unit to determine that the given thread, for which the memory controller access monitor unit is to monitor the accesses to both the first and second memory controllers, is a memory access intensive thread. 
     
     
         8 . The apparatus of  claim 1 , wherein the memory controller access monitor unit is to monitor at least one of: (a) a proportion of instructions processed by the given thread that are cache misses; and (b) a count of cycle stalls for the given thread. 
     
     
         9 . The apparatus of  claim 1 , wherein the first thread processor is coupled with the first memory controller through a plurality of intervening thread processors coupled between the first thread processor and the first memory controller. 
     
     
         10 . The apparatus of  claim 1 , wherein the thread processors comprise a plurality of cores, and wherein the thread processor selector unit is to select the second thread processor based in part on a queuing delay that is to incorporate a queuing delay of an intervening thread processor coupled between the second thread processor and the first memory controller. 
     
     
         11 . The apparatus of  claim 1 , further comprising a thread installation unit to install the thread on the second thread processor, wherein the thread installation unit comprises logic of an integrated circuit having the second thread processor. 
     
     
         12 . A system comprising:
 a first memory;   a second memory;   a first memory controller coupled with the first memory to provide access to the first memory;   a second memory controller coupled with the second memory to provide access to the second memory;   a plurality of thread processors of a chip multi-processor (CMP) coupled with the first and second memory controllers, the thread processors to run a plurality of threads that are to access the first and second memories through the first and second memory controllers; and   an operating system module stored in a memory, the operating system module to install a thread on a thread processor of the plurality of thread processor of the CMP based at least in part on a relative proportion of accesses by the thread to both the first and second memories, wherein the thread processor on which the thread is to be installed is coupled with the first memory controller through at least one intervening thread processor and is coupled with the second memory controller through at least one intervening thread processor.   
     
     
         13 . The system of  claim 12 , wherein an average memory access latency for accesses by the thread from the thread processor to the first and second memories is to be less than from any other thread processor. 
     
     
         14 . The system of  claim 12 , wherein the operating system module is to migrate an existing thread of the plurality of threads from the thread processor to another thread processor of the plurality of thread processors prior to installing the thread on the thread processor. 
     
     
         15 . An apparatus comprising:
 a plurality of thread processors of a multi-core processor to run a plurality of threads;   a first memory controller coupled with the plurality of thread processors, the first memory controller to couple with and to provide access to a first memory;   a second memory controller coupled with the plurality of thread processors, the second memory controller to couple with and to provide access to a second memory;   a thread processor selection logic to:   monitor accesses, by a given thread of the plurality of threads that is to run on the first thread processor, to both the first memory controller and the second memory controller; and   select a second thread processor of the plurality of thread processors of the multi-core processor for a thread based on the monitored accesses by the given thread to both the first memory controller and the second memory controller, wherein the second thread processor is coupled with the first memory controller through at least one intervening thread processor and is coupled with the second memory controller through at least one intervening thread processor.   
     
     
         16 . The apparatus of  claim 15 , wherein the thread processor selection logic is to select the second thread processor to improve overall memory access latency from the second thread processor to the first and second memories. 
     
     
         17 . The apparatus of  claim 15 , wherein the thread processor selection logic is to select the second thread processor based on a relative proportion of the monitored accesses to the first and second memory controllers. 
     
     
         18 . The apparatus of  claim 15 , wherein the thread processor selection logic is to select the second thread processor based on a first queuing delay, which is to incorporate a queuing delay of an intervening thread processor, and which is to be associated with memory accesses to the first memory and a second queuing delay associated with memory accesses to the second memory. 
     
     
         19 . The apparatus of  claim 15 , wherein the thread processor selection logic is to select the second thread processor for the given thread for which the memory controller access monitor unit is to monitor the accesses to both the first and second memory controllers, and further comprising a thread migration initiation unit to initiate migration of the given thread from the first thread processor to the second thread processor.