Two address translations from a single table look-asside buffer read

Abstract

A streaming engine employed in a digital data processor specifies a fixed read only data stream. An address generator produces virtual addresses of data elements. An address translation unit converts these virtual addresses to physical addresses by comparing the most significant bits of a next address N with the virtual address bits of each entry in an address translation table. Upon a match, the translated address is the physical address bits of the matching entry and the least significant bits of address N. The address translation unit can generate two translated addresses. If the most significant bits of address N+1 match those of address N, the same physical address bits are used for translation of address N+1. The sequential nature of the data stream increases the probability that consecutive addresses match the same address translation entry and can use this technique.

What is claimed is: 
     
         1 . An address translation unit comprising:
 an address translation table storing a plurality of entries each including a set of a first plurality of most significant virtual address bits and a set of a second plurality of most significant physical address bits;   a first comparator connected to said address generator and said address translation table, said comparator comparing said first plurality of most significant bits of said next sequential address N with said first plurality of most significant virtual address bits of each entry of said address translation table, said comparator upon detecting a match generating an entry select signal indicating which entry matched;   a multiplexer connected to said address translation table and said comparator, said multiplexer having plural input each receiving said second plurality of most significant physical address bits of a corresponding entry of said address translation table, an output and a control input receiving said entry select signal, said multiplexer outputting said second plurality of most significant physical address bits of one entry of said address translation table indicated by said entry select signal;   a first concatenator connected to said address generator and said multiplexer forming a first physical address having a second plurality of most significant bits equal to said second plurality of most significant physical address bits of said entry of said address translation table output by said multiplexer and a third plurality of least significant bits equal to said third plurality of least significant bits of said next sequential address N;   a second comparator connected to said address generator comparing said first plurality of most significant bits of said next sequential address N with said first plurality of most significant bits of said following address N+1; and   a second concatenator connected to said address generator and said multiplexer forming a second physical address having a second plurality of most significant bits equal to said second plurality of most significant physical address bits of said entry of said address translation table output by said multiplexer and a third plurality of least significant bits equal to said third plurality of least significant bits of said following address N+1.   
     
     
         2 . The address translation unit of  claim 1 , further comprising:
 a command queue storing a stream of physical memory addresses corresponding to said stream of virtual memory addresses.   
     
     
         3 . The address translation unit of  claim 2 , wherein:
 said first comparator generates an address N valid signal upon a match between said first plurality of most significant bits of said next sequential address N with said first plurality of most significant virtual address bits of one entry of said address translation table; and   said command queue is connected to said first comparator and stores a physical memory addresses corresponding address N only if said address N valid signal indicates address N is valid.   
     
     
         4 . The address translation unit of  claim 2 , wherein:
 said second comparator generates an address N+1 valid signal upon a match between said first plurality of most significant bits of said next sequential address N with said first plurality of most significant virtual address bits of following address N+1; and   said command queue is further connected to said second comparator and stores a physical memory addresses corresponding address N+1 only if said address N+1 valid signal indicates address N+1 is valid.   
     
     
         5 . The address translation unit of  claim 1 , wherein:
 if said first comparator does not detect a match between said first plurality of most significant bits of said next sequential address N with said first plurality of most significant virtual address bits of any entry of said address translation table, said first comparator requests an address translation table entry corresponding to first plurality of most significant bits of said next sequential address N from a memory.   
     
     
         6 . The address translation unit of  claim 1 , wherein:
 each entry of said address translation table further includes a permission field indicating whether a portion of memory corresponding to said entry is readable or writable; and   said first comparator detects a match only if said permission bits of said entry indicate said corresponding portion of memory is readable.   
     
     
         7 . The address translation unit of  claim 1 , wherein:
 each entry of said address translation table further includes a permission field indicating whether a portion of memory corresponding to said entry is Normal or a Device; and   said first comparator detects a match only if said permission bits of said entry indicate said corresponding portion of memory is Normal.   
     
     
         8 . The address translation unit of  claim 1 , wherein:
 each entry of said address translation table further includes a permission field indicating a security status of a portion of memory corresponding to said entry; and   said first comparator detects a match only if said permission bits of said entry indicate a security status corresponding to a current privilege execution mode.   
     
     
         9 . A digital data processor comprising:
 an instruction memory storing instructions each specifying a data processing operation and at least one data operand field;   an instruction decoder connected to said instruction memory for sequentially recalling instructions from said instruction memory and determining said specified data processing operation and said specified at least one operand;   at least one functional unit connected said instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by said instruction decoder and storing results;   a streaming engine connected to said instruction decoder operable in response to a stream start instruction to recall from memory a stream of an instruction specified sequence of a plurality of data elements, said streaming engine including
 an address generator for generating stream of virtual memory addresses corresponding to said stream of an instruction specified sequence of a plurality of data elements, said stream of addresses including a next sequential address N and a following address N+1, 
 an address translation unit connected to said address generator for receiving said stream of virtual memory addresses and converting each virtual memory address into a corresponding physical memory address, said address translation unit comprising:
 an address translation table storing a plurality of entries each including a set of a first plurality of most significant virtual address bits and a set of a second plurality of most significant physical address bits, 
 a first comparator connected to said address generator and said address translation table, said comparator comparing said first plurality of most significant bits of said next sequential address N with said first plurality of most significant virtual address bits of each entry of said address translation table, said comparator upon detecting a match generating an entry select signal indicating which entry matched, 
 a multiplexer connected to said address translation table and said comparator, said multiplexer having plural input each receiving said second plurality of most significant physical address bits of a corresponding entry of said address translation table, an output and a control input receiving said entry select signal, said multiplexer outputting said second plurality of most significant physical address bits of one entry of said address translation table indicated by said entry select signal, 
 a first concatenator connected to said address generator and said multiplexer forming a first physical address having a second plurality of most significant bits equal to said second plurality of most significant physical address bits of said entry of said address translation table output by said multiplexer and a third plurality of least significant bits equal to said third plurality of least significant bits of said next sequential address N, 
 a second comparator connected to said address generator comparing said first plurality of most significant bits of said next sequential address N with said first plurality of most significant bits of said following address N+1, and 
 a second concatenator connected to said address generator and said multiplexer forming a second physical address having a second plurality of most significant bits equal to said second plurality of most significant physical address bits of said entry of said address translation table output by said multiplexer and a third plurality of least significant bits equal to said third plurality of least significant bits of said following address N+1, 
 
 a stream head register storing a data element of said stream next to be used by said at least one functional unit, 
   wherein said at least one functional unit is responsive to a stream operand instruction to receive at least one operand from said stream head register.   
     
     
         10 . The digital data processor of  claim 9 , wherein:
 said stream engine further including
 a command queue connected to said address translation unit storing a stream of physical memory addresses corresponding to said stream of virtual memory addresses. 
   
     
     
         11 . The digital data processor of  claim 10 , wherein:
 said first comparator generates an address N valid signal upon a match between said first plurality of most significant bits of said next sequential address N with said first plurality of most significant virtual address bits of one entry of said address translation table; and   said command queue is further connected to said first comparator and stores a physical memory addresses corresponding address N only if said address N valid signal indicates address N is valid.   
     
     
         12 . The digital data processor of  claim 10 , wherein:
 said second comparator generates an address N+1 valid signal upon a match between said first plurality of most significant bits of said next sequential address N with said first plurality of most significant virtual address bits of following address N+1; and   said command queue is further connected to said second comparator and stores a physical memory addresses corresponding address N+1 only if said address N+1 valid signal indicates address N+1 is valid.   
     
     
         13 . The digital data processor of  claim 9 , wherein:
 if said first comparator does not detect a match between said first plurality of most significant bits of said next sequential address N with said first plurality of most significant virtual address bits of any entry of said address translation table, said first comparator requests an address translation table entry corresponding to first plurality of most significant bits of said next sequential address N from a memory.   
     
     
         14 . The digital data processor of  claim 9 , wherein:
 each entry of said address translation table further includes a permission field indicating whether a portion of memory corresponding to said entry is readable or writable; and   said first comparator detects a match only if said permission bits of said entry indicate said corresponding portion of memory is readable.   
     
     
         15 . The digital data processor of  claim 9 , wherein:
 each entry of said address translation table further includes a permission field indicating whether a portion of memory corresponding to said entry is Normal or a Device; and   said first comparator detects a match only if said permission bits of said entry indicate said corresponding portion of memory is Normal.   
     
     
         16 . The digital data processor of  claim 9 , wherein:
 each entry of said address translation table further includes a permission field indicating a security statue of a portion of memory corresponding to said entry; and   said first comparator detects a match only if said permission bits of said entry indicate a security status corresponding to a current privilege execution mode.   
     
     
         17 . The digital data processor of  claim 9 , wherein:
 said instruction specified sequence of a plurality of data elements includes an instruction specified number of data elements having an instruction specified data size.   
     
     
         18 . The digital data processor of  claim 17 , wherein:
 said stream head register is divided into lanes of said element data size; and   said streaming engine stores one data element of said stream in each lane of said stream head register.   
     
     
         19 . The digital data processor of  claim 18 , wherein:
 if there are fewer remaining data elements than lanes of said stream head register, said streaming engine stores all 0's in excess lanes.   
     
     
         20 . The digital data processor of  claim 9 , wherein:
 said instruction specified sequence of a plurality of said data elements each have the same data size.   
     
     
         21 . The digital data processor of  claim 9 , wherein:
 said instruction specified sequence of a plurality of data elements each have an instruction specified data type.   
     
     
         22 . The digital data processor of  claim 9 , further comprising:
 a data coherence unit connected to said streaming engine and to the memory, said data coherence unit operable to assure said stream is coherent with all writes to memory before said stream start instruction.   
     
     
         23 . The digital data processor of  claim 22 , further comprising:
 said data coherence unit does not assure said stream is coherent with all writes to memory after said stream start instruction.   
     
     
         24 . The digital data processor of  claim 22 , further comprising:
 said streaming engine is responsive to a stream end instruction to stop recall of data; and   said instruction memory includes instructions controlling said at least one functional unit to avoid memory writes to memory addresses within a block of memory including said instruction specified plurality of data elements of said stream during an interval between a corresponding stream start instruction and a corresponding stream end instruction.   
     
     
         25 . The digital data processor of  claim 9 , further comprising:
 said streaming engine is responsive to a stream end instruction to stop recall of said data elements.   
     
     
         26 . The digital data processor of  claim 9 , further comprising:
 said streaming engine is responsive to recall of all data elements in said stream to stop recall of said data elements.   
     
     
         27 . The digital data processor of  claim 9 , wherein:
 said stream operand instruction includes a stream operand read only instruction and a stream operand read and increment instruction;   said at least one operational unit receiving as an operand data stored in said stream head register in response to a stream operand read only instruction and a stream operand read and increment instruction; and   said stream engine storing a next fetched data element in said stream head register in response to a stream operand read and increment instruction.   
     
     
         28 . The digital data processor of  claim 27 , further comprising:
 a data register file including a plurality of data registers designated by register number storing data;   wherein said at least one functional unit is connected to said data register file and stores said results in an instruction specified data register; and   wherein said instruction decoder is operable to
 decode an instruction having a data operand field having a first subset of bit codings to supply data stored in a corresponding data register to a corresponding functional unit, 
 decode an instruction having a data operand field having a predetermined read bit coding to supply said data stored in said stream head register to said corresponding functional unit, 
 decode an instruction having a data operand field having a predetermined read/advance bit coding to supply said data stored in said stream head register to said corresponding functional unit and to advance said streaming engine by storing a next sequential data element of said stream in said stream head register. 
   
     
     
         29 . The digital data processor of  claim 9 , further comprising:
 a level one data cache connected to said at least one functional unit temporarily storing data for manipulation by said at least one functional unit, said level one data cache servicing said at least one functional unit memory reads and writes if corresponding data is stored therein (cache hit), otherwise (cache miss) referring said at least one functional unit memory reads and writes to a higher level memory; and   a level two cache connected to said level one data cache and to said streaming engine, said level two cache temporarily storing data for manipulation by said at least one functional unit, said level two cache servicing level one data cache misses on memory reads and writes and streaming engine memory reads if corresponding data is stored therein (cache hit), otherwise (cache miss) referring said at least one functional unit memory reads and writes and streaming engine reads to a higher level memory.