Memory equipped with information retrieval function, method for using same, device, and information processing method

Abstract

CPUs are not effective for search processing for information on a memory. Content-addressable memories (CAMs) are effective for information searches, but it is difficult to build a large-capacity memory usable for big data using the CAMs. A large-capacity memory may be turned into an active memory having an information search capability comparable to that of a content-addressable memory (CAM) by incorporating an extremely small, single-bit-based parallel logical operation unit into a common memory. With this memory, a super fast in-memory database capable of fully parallel searches may be realized.

What is claimed is: 
     
         1 . A memory capable of reading and writing information, provided with an information search function,
 (1) wherein the memory has one word bit width of n and N word addresses, that is a storage cell structure of N×n bits,   (2) the memory comprising: a logical operation unit having a set of n bits for the entirety of the memory;   (3) a function to enter (substitute) storage cell information having the one word bit width of n into the logical operation unit having the set of n bits, and logically operate the storage cell information, wherein the storage cell information is repeatedly selected/specified from among the N word addresses; and   (4) a function to output contents of the logical operation unit.   
     
     
         2 . The memory provided with the information search function of  claim 1 , wherein the logical operation unit is configured to be capable of logical storage, logical product, logical sum, logical negation, exclusive logic or any combinatorial operation thereof between single bits of the entered (substituted) memory storage cell information having the one word bit width of n. 
     
     
         3 . The memory provided with the information search function of  claim 1 , wherein the logical operation unit is provided with a shift register function. 
     
     
         4 . The memory provided with the information search function of  claim 1 , wherein the memory performs an exact match search for a data value and a range search for data values using the logical storage, logical product, logical sum, logical negation, exclusive logic or any combinatorial operation thereof. 
     
     
         5 . The memory provided with the information search function of  claim 1 , wherein the memory performs an addition or a subtraction of data values using the logical storage, logical product, logical sum, logical negation, exclusive logic or any combinatorial operation thereof. 
     
     
         6 . The memory provided with the information search function of  claim 1 , wherein the memory is integrated with a semiconductor device of another type such as a CPU. 
     
     
         7 . The memory provided with the information search function of  claim 1 , wherein the memory is implemented in an FPGA. 
     
     
         8 . A method for using the memory provided with the information search function of  claim 1 , comprising the step of assigning a database record to any one of columns within the one word bit width of n to generate a database, wherein a total bit number of fields per record of the database equals the number of word addresses N. 
     
     
         9 . A method for using the memory provided with the information search function of  claim 1 , comprising the step of:
 connecting for use, memories each provided with the information search function   (1) in series, in parallel or in series and parallel;   (2) hierarchically; or   (1) or (2).   
     
     
         10 . A device including the memory of  claim 1 . 
     
     
         11 . An information processing method comprising the step of repeating logical product, logical sum, logical negation, exclusive logic or any combinatorial logical operation thereof between single bits of the memory storage cell information within the memory to thereby obtain a prescribed operation result. 
     
     
         12 . The information processing method of  claim 11 , further comprising the step of performing the logical operation in parallel between the single bits of the information.