Solder composition and semiconductor package including the same

Abstract

Solder compositions for semiconductor fabrication are provided that include silver (Ag) of 3.0 wt. % to 4.0 wt. %, copper (Cu) of 0.75 wt. % to 1.0 wt. %, nickel (Ni) of 0.08 wt. % to 1.0 wt. %, and tin (Sn) of 94 wt. % to 96.17 wt. %, or that include bismuth (Bi) of 0.3 wt. % to 2.0 wt. % in place of a portion of the tin (Sn) in the solder composition; and, semiconductor packages are also provided that use the solder compositions for bonding one or more components of the semiconductor packages to each other.

1 . A solder composition comprising:
 silver (Ag) of 3.0 wt. % to 4.0 wt. %;   copper (Cu) of 0.75 wt. % to 1.0 wt. %;   nickel (Ni) of 0.08 wt. % to 1.0 wt. %; and   tin (Sn) of 94 wt. % to 96.17 wt. %.   
     
     
         2 . The solder composition of  claim 1 , wherein a content of silver (Ag) in the solder composition ranges from 3.0 wt. % to 3.5 wt. %. 
     
     
         3 . The solder composition of  claim 1 , wherein a content of copper (Cu) in the solder composition ranges from 0.75 wt. % to 0.9 wt. %. 
     
     
         4 . The solder composition of  claim 1 , wherein a content of nickel (Ni) in the solder composition ranges from 0.08 wt. % to 0.5 wt. %. 
     
     
         5 . The solder composition of  claim 1 , further comprising:
 bismuth (Bi) of 0.3 wt. % to 2.0 wt. %, which is substituted for a portion of the tin (Sn) in the solder composition.   
     
     
         6 . The solder composition of  claim 5 , wherein a content of bismuth (Bi) in the solder composition ranges from 0.5 wt. % to 1.0 wt. %. 
     
     
         7 . The solder composition of  claim 5 , wherein at least a portion of the bismuth (Bi) in the solder composition is soluble in a grain boundary between grains of the solder composition. 
     
     
         8 . The solder composition of  claim 7 , wherein a growth rate of a grain size of the solder composition after a reflow process ranges from 0% to 15% resulting in relatively smaller solder composition grain sizes in comparison with a comparable solder composition that does not include nickel (Ni) or bismuth (Bi). 
     
     
         9 . A semiconductor package comprising:
 a first interconnection substrate having a top first substrate surface and a bottom first substrate surface opposite to the top first substrate surface;   a first semiconductor chip disposed on the top first substrate surface, the first semiconductor chip having a first chip surface facing the top first substrate surface and a second chip surface opposite to the first chip surface; and   first connection terminals disposed between the first interconnection substrate and the first semiconductor chip,   wherein the first semiconductor chip is mounted on the first interconnection substrate through the first connection terminals by a flip-chip bonding method, and   wherein the first connection terminals include a solder composition consisting essentially of about 3.0 wt. % to about 4.0 wt. % silver (Ag), about 0.75 wt. % to about 1.0 wt. % copper (Cu), about 0.08 wt. % to about 1.0 wt. % nickel (Ni), and about 94 wt. % to about 96.17 wt. % tin (Sn).   
     
     
         10 . The semiconductor package of  claim 9 , wherein the first connection terminals further include bismuth of 0.3 wt. % to 2.0 wt. %, which is substituted for a portion of the tin (Sn) in the solder composition. 
     
     
         11 . The semiconductor package of  claim 10 , wherein: the first interconnection substrate comprises first solder pads disposed on the top first substrate surface,
 the first semiconductor chip comprises second solder pads disposed on the first chip surface, and   the first connection terminals are disposed between the first solder pads and the second solder pads.   
     
     
         12 . The semiconductor package of  claim 11 , wherein the first solder pads and the second solder pads include copper (Cu), nickel (Ni), or gold (Au). 
     
     
         13 . The semiconductor package of  claim 9 , further comprising:
 a second interconnection substrate disposed on the first semiconductor chip;   a second semiconductor chip mounted on the second interconnection substrate;   and   second connection terminals disposed between the first interconnection substrate and the second interconnection substrate and disposed around the first semiconductor chip,   wherein the first interconnection substrate is electrically connected to the second interconnection substrate through the second connection terminals, and   wherein the second connection terminals include the same solder composition as the first connection terminals.   
     
     
         14 . The semiconductor package of  claim 13 , wherein the first semiconductor chip is a logic chip, and
 wherein the second semiconductor chip is a memory chip that is mounted on the second interconnection substrate by a flip-chip bonding method or a wire bonding method.   
     
     
         15 . The semiconductor package of  claim 9 , further comprising:
 a main substrate disposed under the first interconnection substrate; and   external connection terminals disposed between the main substrate and the first interconnection substrate,   wherein the main substrate is electrically connected to the first interconnection substrate through the external connection terminals provided on the bottom first substrate surface, and wherein the external connection terminals include the same solder composition used for the first connection terminals.   
     
     
         16 . A solder composition consisting essentially of:
 silver (Ag) of about 3.0 wt. % to 4.0 wt. %;   copper (Cu) of about 0.75 wt. % to 1.0 wt. %;   nickel (Ni) of about 0.08 wt. % to 1.0 wt. %; and   tin (Sn) of about 94 wt. % to 96.17 wt. %.   
     
     
         17 . The solder composition of  claim 16  additionally including about 0.3 wt. % to 2.0 wt. % of bismuth (Bi). 
     
     
         18 . The semiconductor package of  claim 13 , further comprising:
 a main substrate disposed under the first interconnection substrate; and   external connection terminals disposed between the main substrate and the first interconnection substrate,   wherein the main substrate is electrically connected to the first interconnection substrate through the external connection terminals provided on the bottom first substrate surface, and   wherein the external connection terminals include the same solder composition as the first connection terminals.   
     
     
         19 . A method of preparing a semiconductor device comprising the steps of:
 providing a first interconnection substrate having a top first substrate surface with one or more first solder pads disposed thereon;   providing a first semiconductor chip having a first chip surface with one or more second solder pads disposed thereon at locations such that the second solder pads align with corresponding first solder pads when the first semiconductor chip is connected with the first interconnection substrate; and,   connecting the second solder pads with the corresponding first solder pads using the solder composition of  claim 16 .   
     
     
         20 . The method of  claim 19  wherein the first solder pads and the second solder pads comprise copper (Cu), nickel (Ni) and/or gold (Au).