Wiring substrate, semiconductor package having the wiring substrate, and manufacturing method thereof

Abstract

Provided is a wiring substrate and its manufacturing method in which a thick wiring layer capable of being applied with a large current and a thin wiring layer capable of being subjected to microfabrication coexist in the same layer. The wiring substrate includes: an insulating film located over a first wiring and having a via; and a second wiring over the insulating film. The second wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is in direct contact with the first wiring in the via. A thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via.

What is claimed is: 
     
         1 . A wiring substrate comprising:
 a first wiring;   an insulating film over the first wiring, the insulating film comprising a via; and   a second wiring over the insulating film,   wherein the second wiring has a stacked structure including:
 a first layer; and 
 a second layer covering the first layer, 
   wherein the second layer is in direct contact with the first wiring in the via, and   wherein a thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via.   
     
     
         2 . The wiring substrate according to  claim 1 ,
 wherein the thickness of the second layer in the via is larger than the thickness of the second layer in the region overlapping with the first layer.   
     
     
         3 . The wiring substrate according to  claim 1 ,
 wherein a thickness of the first layer is larger than the thickness of the second layer in the region overlapping with the first layer.   
     
     
         4 . The wiring substrate according to  claim 1 ,
 wherein a top surface of the insulating film has a depression between the via and the first layer.   
     
     
         5 . A wiring substrate comprising:
 a first wiring;   an insulating film over the first wiring, the insulating film comprising a via; and   a second wiring over the insulating film,   wherein the second wiring has a stacked structure including:
 a second layer in direct contact with the first wiring in the via; and 
 a first layer over and electrically connected to the second layer, and 
   wherein a thickness of the second layer in a region overlapping with the insulating film is different from a thickness of the first layer in the via.   
     
     
         6 . The wiring substrate according to  claim 5 ,
 wherein a thickness of the second layer in the via is larger than the thickness of the second layer in the region overlapping with the insulating film.   
     
     
         7 . The wiring substrate according to  claim 5 ,
 wherein the thickness of the first layer is larger than the thickness of the second layer in the region overlapping with the insulating film.   
     
     
         8 . A semiconductor package comprising:
 a semiconductor device comprising a terminal;   an insulating film over the terminal, the insulating film comprising a via; and   a wiring over the insulating film,   wherein the wiring has a stacked structure including:
 a first layer; and 
 a second layer covering the first layer; 
   wherein the second layer is in direct contact with the terminal in the via, and   wherein a thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via.   
     
     
         9 . The semiconductor package according to  claim 8 ,
 wherein the thickness of the second layer in the via is larger than the thickness of the second layer in the region overlapping with the first layer.   
     
     
         10 . The semiconductor package according to  claim 8 ,
 wherein a thickness of the first layer is larger than the thickness of the second layer in the region overlapping with the first layer.   
     
     
         11 . The semiconductor package according to  claim 8 ,
 wherein a top surface of the insulating film has a depression between the via and the first layer.   
     
     
         12 . A semiconductor package comprising:
 a semiconductor device comprising a terminal;   an insulating film over the terminal, the insulating film comprising a via; and   a wiring over the insulating film,   wherein the wiring has a stacked structure including:
 a second layer in direct contact with the terminal in the via; and 
 a first layer over and electrically connected to the second layer, and 
   wherein a thickness of the second layer in a region overlapping with the insulating film is different from a thickness of the second layer in the via.   
     
     
         13 . The semiconductor package according to  claim 12 ,
 wherein the thickness of the second layer in the via is larger than the thickness of the second layer in the region overlapping with the insulating film.   
     
     
         14 . The semiconductor package according to  claim 12 ,
 wherein a thickness of the first layer is larger than the thickness of the second layer in the region overlapping with the insulating film.   
     
     
         15 . A manufacturing method of a wiring substrate, the manufacturing method including:
 forming an insulating film over a first wiring; and   forming a second wiring over the insulating film, the second wiring comprising a first layer and a second layer,   wherein the formation of the second wiring includes:
 forming the second layer by bonding a metal plate to the insulating film; 
 exposing the insulating film by forming an opening portion in the second layer; 
 exposing the first wiring by forming a via in the insulating film; and 
 forming the first layer with an electroplating method so that the first layer is located over and in direct contact with the first wiring and the second layer. 
   
     
     
         16 . The manufacturing method of a wiring substrate according to  claim 15 ,
 wherein a thickness of the second layer in the via is larger than a thickness of the second layer in a region overlapping with the first layer.   
     
     
         17 . The manufacturing method of a wiring substrate according to  claim 15 ,
 wherein a thickness of the first layer is larger than a thickness of the second layer in a region overlapping with the first layer.   
     
     
         18 . A manufacturing method of a wiring substrate, the manufacturing method including:
 forming an insulating film over a first wiring;   exposing the first wiring by forming a via in the insulating film; and   forming a second wiring over the insulating film, the second wiring comprising a first layer and a second layer,   wherein the formation of the second wiring includes:
 forming the second layer with an electroplating method so that the second layer is located over and in contact with the first wiring and the insulating film; and 
 forming the first layer by disposing a metal plate over the second layer so that the first layer is electrically connected to the second layer. 
   
     
     
         19 . The manufacturing method of a wiring substrate according to  claim 18 ,
 wherein a thickness of the second layer in the via is larger than a thickness of the second layer in a region overlapping with the insulating film.   
     
     
         20 . The manufacturing method of a wiring substrate according to  claim 18 ,
 wherein a thickness of the first layer is larger than a thickness of the second layer in a region overlapping with the insulating film.   
     
     
         21 . A manufacturing method of a semiconductor package, the manufacturing method comprising:
 forming a semiconductor device over a first wiring, the semiconductor device comprising a first terminal and a second terminal;   forming an insulating film over the second terminal; and   forming a second wiring over the insulating film, the second wiring including a first layer and a second layer,   wherein the formation of the second wiring includes:
 forming the second layer by bonding a metal plate to the insulating film; 
 exposing the insulating film by forming an opening portion in the second layer; 
 exposing the first wiring by forming a via in the insulating film; and 
 forming the first layer with an electroplating method so that the first layer is located over and in direct contact with the first wiring and the second layer. 
   
     
     
         22 . The manufacturing method of a semiconductor package according to  claim 21 ,
 wherein a thickness of the second layer in the via is larger than a thickness of the second layer in a region overlapping with the first layer.   
     
     
         23 . The manufacturing method of a semiconductor package according to  claim 22 ,
 wherein a thickness of the first layer is larger than a thickness of the second layer in the region overlapping with the first layer.   
     
     
         24 . The manufacturing method of a semiconductor package according to  claim 22 ,
 wherein a top surface of the insulating film has a depression between the via and the first layer.   
     
     
         25 . A manufacturing method of a semiconductor package, the manufacturing method comprising:
 forming a semiconductor device over the first wiring, the semiconductor device comprising a first terminal and a second terminal;   forming an insulating film over the second terminal; and   forming a second wiring over the insulating film, the second wiring including a first layer and a second layer,   wherein the formation of the second wiring comprises:
 forming the second layer with an electroplating method so that the second layer is located over and in contact with the first wiring and the insulating film; and 
 forming the first layer by disposing a metal plate over the second layer so that the first layer is electrically connected to the second layer. 
   
     
     
         26 . The manufacturing method of a wiring substrate according to  claim 25 ,
 wherein a thickness of the second layer in the via is larger than a thickness of the second layer in a region overlapping with the insulating film.   
     
     
         27 . The manufacturing method of a wiring substrate according to  claim 25 ,
 wherein a thickness of the first layer is larger than a thickness of the second layer in a region overlapping with the insulating film.