Electronic device, assembly and methods of manufacturing an electronic device including a vertical trench capacitor and a vertical interconnect

Abstract

A semiconductor substrate comprises both vertical interconnects and vertical capacitors with a common dielectric layer. The substrate can be suitably combined with further devices to form an assembly. The substrate can be made in etching treatments including a first step on the one side, and then a second step on the other side of the substrate.

1 . A method of manufacturing an electronic device comprising a semiconductor substrate having a first and a second side and provided with a capacitor and a vertical interconnect extending from the first to the second side, on which first side the capacitor is present, said method comprising the steps of:
 providing first trenches in the substrate including the step   
       of etching from the first side of the substrate;
 providing second trenches in the substrate by etching from one side of the substrate and opening the second trenches by removing material from the opposite side of the substrate; 
 providing said first trenches with a conductive surface; 
 applying a layer of dielectric material on the substrate, 
 
       covering at least the first side of the substrate and the inner faces of the first and second trenches; and
 applying electrically conductive material in the first 
 
       trenches and in the second trenches, which conductive material of the first trenches together with the layer of dielectric material and the conductive surface forms the capacitor, and which conductive material of the second trenches forms the vertical interconnects. 
     
     
         2 . A method as claimed in  claim 1 , wherein the first trenches and the second trenches are etched in a single step, said first trenches having a smaller diameter than the second trenches leading to the through-holes, with the result that the second trenches will extend further into the substrate than the first trenches, said trenches having inner faces. 
     
     
         3 . A method as claimed in  claim 2 , characterized in that the step of applying conductive material in the second trenches comprises the steps of applying a seed layer and electroplating. 
     
     
         4 . A method as claimed in  claim 2 , characterized in that a plurality of second trenches are neighbouring and mutually interconnected so as to form a single vertical interconnect. 
     
     
         5 . A method as claimed in  claim 4 , wherein the electrically conductive material applied in the first and the second trenches is polysilicon. 
     
     
         6 . A method as claimed in  claim 1 , wherein the step of removing material for opening the second trenches comprises the step of wet-chemical etching to form a cavity, said cavity having a larger diameter than the second trenches. 
     
     
         7 . A method as claimed in  claim 1 , wherein the second trenches are formed by wet-chemical etching from the second side of the substrate before provision of the first trenches, said second trenches being shaped as cavities and have a larger diameter than the first trenches. 
     
     
         8 . A method as claimed in  claim 7 , wherein the second trenches are opened by etching in the same step as the etching of the first trenches. 
     
     
         9 . A method as claimed in  claim 7 , wherein the second trenches extend up to the first side of the semiconductor substrate and are covered by an etch-stop layer provided on the first side of the substrate. 
     
     
         10 . An electronic device comprising:
 a semiconductor substrate having a first side and a second side;   a plurality of trenches on the first side of the substrate, each of the trenches extending into the substrate from the first side to a depth;   conductive material lining each of the trenches;   a vertical interconnect that extends through the substrate from the first side to the second side, the vertical interconnect having walls;   a single deposition layer of dielectric material on the first and second sides of the substrate, on the conductive material lining each of the trenches, and on the walls of the vertical interconnect.   
     
     
         11 . The electronic device of  claim 10 , wherein the vertical interconnect has a first part and a second part, the first part extending from the first side of the substrate to the second part, the second part extending from the second side of the substrate to the first part and being wider than the first part. 
     
     
         12 . The electronic device of  claim 10 , wherein the vertical interconnect includes a plurality of parallel trenches. 
     
     
         13 . The electronic device of  claim 11 , wherein the first part of the vertical interconnect includes a plurality of parallel trenches each of which extends from the first side of the substrate to the second part of the vertical interconnect. 
     
     
         14 . The electronic device of  claim 10 , wherein the plurality of trenches form a vertical trench capacitor. 
     
     
         15 . The electronic device of  claim 10 , wherein the single deposition layer of dielectric material is on walls of the vertical interconnect that oppose one another, with the vertical interconnect extending uninterrupted between the walls. 
     
     
         16 . The electronic device of  claim 10 , further including a second conductive material in the trenches, the second conductive material being separated from said conductive material lining each of the trenches by the single deposition layer of dielectric material on the conductive material lining each of the trenches, the single deposition layer of dielectric material being on opposing vertical sidewalls of the second conductive material, the second conductive material, single deposition layer of dielectric material and said conductive material lining each of the trenches forming a vertical capacitor. 
     
     
         17 . An electronic device comprising:
 a semiconductor substrate having a first side and a second side and a high-ohmic   
       zone;
 a vertical trench capacitor on the first side of the substrate and including a 
 
       plurality of trenches having first and second conductive surfaces;
 a vertical interconnect that extends through the substrate from the first side to the second side; 
 a planar capacitor on the first side of the substrate, the high-ohmic zone separating the planar capacitor from the vertical trench capacitor; and 
 a single-deposition layer of dielectric material located between the first and second conductive surfaces of the vertical trench capacitor, between conductive plates of the planar capacitor, and configured and arranged to insulate the vertical interconnect from the substrate.