Low-latency timing control

Abstract

A timing control system includes one or more device processors operatively coupled to one or more devices, a counter connected to the device processor(s), and a plurality of timing registers operatively coupled to the counter, each of the timing registers configured to store a value indicating a time at which an event is to be initiated at a corresponding one of the device(s). The system also includes a pulse generator operatively coupled to the counter and the timing registers, the pulse generator configured to generate one or more associated general-purpose input/output (GPIO) output signals, and send to each of the one or more devices an associated GPIO output signal to initiate the event at a plurality of the one or more devices in coordination with one another or to initiate the event at one of the one or more devices in coordination with another event at that device.

1 - 20 . (canceled) 
     
     
         21 . A timing control system comprising:
 one or more device processors operatively coupled to one or more cameras and configured to receive information from each of the one or more cameras;   a counter having a low-latency interface to the one or more device processors;   a plurality of timing registers useable by the counter, each of the plurality of timing registers configured to store a value indicating a time at which an event is to be initiated at a corresponding one of the one or more cameras; and   a pulse generator cooperating with the counter and the plurality of timing registers, the pulse generator configured to:
 generate one or more associated general-purpose input/output (GPIO) output signals based at least on determining that a value of the counter has reached a value of one or more of the plurality of timing registers, and 
 send to each of the one or more cameras an associated GPIO output signal to initiate the event at a plurality of the one or more cameras in coordination with one another or to initiate the event at one of the one or more cameras in coordination with another event at the one of the one or more cameras. 
   
     
     
         22 . The timing control system of  claim 21 , wherein the counter is directly connected to the one or more device processors via a low-latency interface. 
     
     
         23 . The timing control system of  claim 21 , wherein, for each of the timing registers, the value of that register is configured to be set to coordinate the initiation of the event at the corresponding camera relative to an initiation of the event at another camera of the two or more cameras. 
     
     
         24 . The timing control system of  claim 21 , wherein the one or more device processors include an image sensor processor and the one or more cameras includes two or more image sensors. 
     
     
         25 . The timing control system of  claim 24 , wherein the event comprises capturing an image with the two or more image sensors, each image sensor capturing a respective image for an associated exposure time. 
     
     
         26 . The timing control system of  claim 25 , wherein, for each of the timing registers, the value of that register is configured to be set to coordinate the initiation of the event at the corresponding camera relative to an initiation of the event at another camera such that the time of each of the timing registers is configured to align a midpoint of the associated exposure time for each of the two or more image sensors to a midpoint of the associated exposure time for one or more other image sensors of the two or more image sensors. 
     
     
         27 . The timing control system of  claim 25 , wherein the image sensor processor is configured to timestamp a received image captured by one of the two or more image sensors with a current value of the counter. 
     
     
         28 . The timing control system of  claim 21 , wherein the one or more cameras comprise an image sensor and a light emitter, the time of each of the timing registers configured to be set to coordinate an image capture event at the image sensor and a light emission event at the light emitter. 
     
     
         29 . The timing control system of  claim 21 , wherein the counter is configured to increment at a frequency that is greater than or equal to 7.8125 MHz. 
     
     
         30 . The timing control system of  claim 21 , wherein the low-latency interface is configured to introduce less than 1 μs of delay in transmission of data between the counter and the device processor. 
     
     
         31 . The timing control system of  claim 21 , wherein each of the plurality of timing registers is configured to store a type of value corresponding to one of a countdown value and an absolute time value, the countdown value comprising a sum of a current value of the counter and a countdown duration. 
     
     
         32 . The timing control system of  claim 31 , wherein one or more of a mode indicating the type of value used in one or more of the plurality of timing registers and the value of one or more of the plurality of timing registers is configured to be set based on a GPIO input signal received from an external device. 
     
     
         33 . A timing control system comprising:
 an image sensor processor configured to receive information from each of a first image sensor and a second image sensor;   a counter having a low-latency interface directly connecting the counter to the image sensor processor;   a first timing register and a second timing register, each of the first and second timing registers useable by the counter, the first timing register configured to store a value indicating a time at which an image is to be captured at the first image sensor and the second timing register configured to store a value indicating a time at which an image is to be captured at the second image sensor, for each of the timing registers, the value of that register configured to be set to coordinate the initiation of the image capture at the corresponding image sensor relative to an initiation of the image capture at the other image sensor; and   a pulse generator cooperating with the counter and the first and second timing registers, the pulse generator configured to:
 generate and send, to the first image sensor, a first general-purpose input/output (GPIO) output signal responsive to determining that a value of the counter has reached the value of the first timing register, and 
 generate and send, to the second image sensor, a second GPIO output signal responsive to determining that a value of the counter has reached the value of the second timing register to initiate the image capture at the first and second image sensors in coordination with one another. 
   
     
     
         34 . The timing control system of  claim 33 , wherein the image capture at the first and second image sensors are configured to be initiated in coordination with one another such that the time of each of the first and second timing registers is configured to be set to align a midpoint of an associated exposure time for each of the first and second image sensors. 
     
     
         35 . The timing control system of  claim 33 , wherein the image sensor processor is configured to read a current value of the counter responsive to receiving an image captured by the first or the second image sensor and generate a header for the image comprising a timestamp based on the current value of the counter. 
     
     
         36 . The timing control system of  claim 33 , wherein a duration between increments of the counter is configured to be less than or equal to 128 ns. 
     
     
         37 . The timing control system of  claim 33 , wherein each of the first and second timing registers is configured to store a selected one of a countdown value and an absolute time value, the countdown value comprising a sum of a current value of the counter and a countdown duration. 
     
     
         38 . A timing control system comprising:
 an image sensor processor configured to receive image data from each of a first image sensor and a second image sensor and to timestamp the received image data, at least one of the first image sensor and the second image sensor being positioned on a head-mounted display device;   a counter having a low-latency interface that provides a direct connection to the image sensor processor;   a first timing register and a second timing register, each of the first and second timing registers useable by the counter, the first timing register storing a value indicating a time at which an image is to be captured at the first image sensor and the second timing register storing a value indicating a time at which an image is to be captured at the second image sensor, for each of the timing registers, the value of that register being set to coordinate an exposure time of the first image sensor to an exposure time of the second image sensor; and   a pulse generator cooperating with the counter and the first and second timing registers, the pulse generator configured to:
 generate and send, to the first image sensor, a first general-purpose input/output (GPIO) output signal responsive to determining that a value of the counter has reached the value of the first timing register, and 
 generate and send, to the second image sensor, a second GPIO output signal responsive to determining that a value of the counter has reached the value of the second timing register to delay initiation of an associated image capture at the second image sensor relative to an initiation of an associated image capture at the first image sensor to align a midpoint of exposure times of the first and second image sensors during the associated image captures at the first and second image sensors. 
   
     
     
         39 . The timing control system of  claim 38 , wherein the image sensor processor is configured to read a value of the counter responsive to receiving image data from one or more of the first and the second image sensors and generate a header for the image data including a timestamp based on the value of the counter. 
     
     
         40 . The timing control system of  claim 39 , wherein the image sensor processor is configured to determine a capture time of the received image based on a receive timestamp and a capture-signal send time.