Semiconductor devices including capacitors and methods of manufacturing the same

Abstract

A semiconductor device includes a substrate, a conductive pattern on the substrate, a lower electrode electrically connected to the conductive pattern, a dielectric layer covering a surface of the lower electrode, a first upper electrode on the dielectric layer, a diffusion barrier on an upper surface of the first upper electrode, and a second upper electrode covering the diffusion barrier, the second upper electrode including a different material from that of the first upper electrode.

1 . A semiconductor device, comprising:
 a substrate;   a conductive pattern on the substrate;   a lower electrode electrically connected to the conductive pattern;   a dielectric layer covering a surface of the lower electrode;   a first upper electrode on the dielectric layer;   a diffusion barrier on an upper surface of the first upper electrode; and   a second upper electrode covering the diffusion barrier, the second upper electrode including a different material from that of the first upper electrode.   
     
     
         2 . The semiconductor device as claimed in  claim 1 , wherein the diffusion barrier includes a metal oxide. 
     
     
         3 . The semiconductor device as claimed in  claim 2 , wherein the diffusion barrier exhibits a conductive oxide property. 
     
     
         4 . The semiconductor device as claimed in  claim 1 , wherein the first upper electrode includes a metal or a metal nitride, and the second upper electrode includes a silicon-based compound. 
     
     
         5 . The semiconductor device as claimed in  claim 4 , wherein the second upper electrode includes at least one of doped polysilicon, doped amorphous silicon, silicon-germanium (SiGe), or doped SiGe. 
     
     
         6 . The semiconductor device as claimed in  claim 4 , wherein the first upper electrode includes titanium nitride. 
     
     
         7 . The semiconductor device as claimed in  claim 1 , wherein the dielectric layer includes a plurality of layers, and at least one layer of the plurality of layers includes a metal oxide. 
     
     
         8 . The semiconductor device as claimed in  claim 7 , wherein the dielectric layer includes at least one of zirconium oxide, hafnium oxide, or aluminum oxide. 
     
     
         9 . The semiconductor device as claimed in  claim 8 , wherein the dielectric layer has a triple-layered structure, and each layer of the triple-layered structure includes at least one of zirconium oxide, hafnium oxide, or aluminum oxide. 
     
     
         10 . The semiconductor device as claimed in  claim 1 , wherein the diffusion barrier continuously and entirely covers the upper surface of the first upper electrode. 
     
     
         11 . The semiconductor device as claimed in  claim 1 , wherein the first upper electrode includes a plurality of pillars, the diffusion barrier sealing seams between the pillars. 
     
     
         12 . The semiconductor device as claimed in  claim 11 , wherein the diffusion barrier has a discontinuous profile sealing the seams. 
     
     
         13 . A semiconductor device, comprising:
 a substrate;   a lower contact on the substrate; and   a capacitor electrically connected to the lower contact, the capacitor including:
 a lower electrode on the lower contact, 
 a dielectric layer on a surface of the lower electrode, 
 a first upper electrode on the dielectric layer, the first upper electrode including a metal or a metal nitride, 
 a diffusion barrier formed from an upper surface of the first upper electrode, and 
 a second upper electrode on the diffusion barrier, the second upper electrode including a non-metallic conductive material. 
   
     
     
         14 . The semiconductor device as claimed in  claim 13 , wherein the lower electrode includes a plurality of lower electrodes, and the second upper electrode is a common plate electrode for the plurality of the lower electrodes. 
     
     
         15 . The semiconductor device as claimed in  claim 14 , wherein the diffusion barrier and the first upper electrode continuously cover the plurality of the lower electrodes and the dielectric layer. 
     
     
         16 .- 31 . (canceled) 
     
     
         32 . A semiconductor device, comprising:
 a conductive pattern on a substrate;   a lower electrode electrically connected to the conductive pattern;   a dielectric layer on the lower electrode;   a first upper electrode on the dielectric layer;   a diffusion barrier on the first upper electrode, the first upper electrode being between the dielectric layer and the diffusion barrier; and   a second upper electrode on the diffusion barrier, the diffusion barrier separating the first and second upper electrodes.   
     
     
         33 . The semiconductor device as claimed in  claim 32 , wherein the diffusion barrier is completely separating the first and second upper electrodes from each other. 
     
     
         34 . The semiconductor device as claimed in  claim 32 , wherein the diffusion barrier covers an entire supper surface of the first upper electrode. 
     
     
         35 . The semiconductor device as claimed in  claim 32 , wherein the diffusion barrier is an oxidized upper portion of the first upper electrode. 
     
     
         36 . The semiconductor device as claimed in  claim 32 , wherein the second upper electrode includes a different material from that of the first upper electrode.