US2017206113A1PendingUtilityA1

Scalable compute fabric

55
Assignee: INTEL CORPPriority: Dec 20, 2012Filed: Mar 31, 2017Published: Jul 20, 2017
Est. expiryDec 20, 2032(~6.4 yrs left)· nominal 20-yr term from priority
Inventors:Scott KrigTeresa Morrison
G06F 9/3873G06F 9/30083G06F 9/5094G06F 9/3897G06F 1/3206G06F 15/8007G06F 9/30079G06F 15/7867G06F 1/3243G06F 15/7839G06F 9/5027G06F 1/324G06F 1/3287G06F 1/3296G06F 9/3867Y02D10/00Y02D30/50
55
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Claims

Abstract

A method and apparatus for providing a scalable compute fabric are provided herein. The method can include determining a workflow for processing by the scalable compute fabric, wherein the workflow is based on an instruction set. A pipeline can be configured dynamically for processing the workflow, and the workflow is executed using the pipeline. A computing device can include a first group of two or more processing cores, a second group of two or more processing cores, and a third group of two or more processing cores. One or more of the first group of two or more processing cores, the second group of two or more processing cores, and the third group of two or more processing cores can power down based on a type of task to be performed.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A computing device comprising:
 a first group of two or more processing cores to perform one or more processing tasks;   a second group of two or more processing cores to perform one or more processing tasks; and   a third group of two or more processing cores to perform one or more processing tasks;   wherein one or more of the first group of two or more processing cores, the second group of two or more processing cores, or the third group of two or more processing cores is to power down based on a type of task to be performed.   
     
     
         2 . The computing device of  claim 1 , wherein one or more of the processing cores is assigned to a respective one of the first group of two or more processing cores, the second group of two or more processing cores, or the third group of two or more processing cores based on specific types of tasks to be performed by the respective one of the first group of two or more processing cores, the second group of two or more processing cores, or the third group of two or more processing cores. 
     
     
         3 . The computing device of  claim 1 , wherein one or more of the first group of two or more processing cores, the second group of two or more processing cores, or the third group of two or more processing cores is to power down based on a type of task to be performed by another of the first group of two or more processing cores, the second group of two or more processing cores, or the third group of two or more processing cores. 
     
     
         4 . The computing device of  claim 1 , wherein the computing device comprises a mobile device. 
     
     
         5 . The computing device of  claim 1 , wherein the computing device comprises a mobile processor. 
     
     
         6 . The computing device of  claim 1 , wherein one or more of the processing cores is powered off in response to a size of a workflow. 
     
     
         7 . The computing device of  claim 1 , wherein all or a portion of one or more of the first group of two or more processing cores, the second group of two or more processing cores, or the third group of two or more processing cores is powered down into a lower power state, a lower clock rate for lower performance, or set to a higher clock rate for higher performance. 
     
     
         8 . The computing device of  claim 1 , wherein at least one processing core is powered off in response to a dynamic configuration of resources into one of the first group of two or more processing cores, the second group of two or more processing cores, or the third group of two or more processing cores to support a workflow. 
     
     
         9 . The computing device of  claim 1 , wherein one or more of the first group of two or more processing cores, the second group of two or more processing cores, or the third group of two or more processing cores comprises an SIMD computing array. 
     
     
         10 . The computing device of  claim 1 , wherein one or more of the first group of two or more processing cores, the second group of two or more processing cores, or the third group of two or more processing cores performs a dynamically configurable function. 
     
     
         11 . The computing device of  claim 1 , wherein one or more of the first group of two or more processing cores, the second group of two or more processing cores, or the third group of two or more processing cores comprises a processing pipeline. 
     
     
         12 . A method comprising:
 arranging processing cores into a first group of two or more processing cores to perform one or more processing tasks, a second group of two or more processing cores to perform one or more processing tasks, and a third group of two or more processing cores to perform one or more processing tasks; and   powering down one or more of the first group of two or more processing cores, the second group of two or more processing cores, or the third group of two or more processing cores based on a type of task to be performed.   
     
     
         13 . The method of  claim 12 , comprising assigning one or more of the processing cores to a respective one of the first group of two or more processing cores, the second group of two or more processing cores, or the third group of two or more processing cores based on specific types of tasks to be performed by the respective one of the first group of two or more processing cores, the second group of two or more processing cores, or the third group of two or more processing cores. 
     
     
         14 . The method of  claim 12 , comprising power down one or more of the first group of two or more processing cores, the second group of two or more processing cores, or the third group of two or more processing cores based on a type of task to be performed by another of the first group of two or more processing cores, the second group of two or more processing cores, or the third group of two or more processing cores. 
     
     
         15 . The method of  claim 12 , wherein the computing device comprises a mobile device. 
     
     
         16 . The method of  claim 12 , wherein the computing device comprises a mobile processor. 
     
     
         17 . The method of  claim 12 , comprising powering off one or more of the processing cores in response to a size of a workflow. 
     
     
         18 . The method of  claim 12 , comprising powering down all or a portion of one or more of the first group of two or more processing cores, the second group of two or more processing cores, or the third group of two or more processing cores into a lower power state, a lower clock rate for lower performance, or set to a higher clock rate for higher performance. 
     
     
         19 . The method of  claim 12 , comprising powering off at least one processing core in response to a dynamic configuration of resources into one of the first group of two or more processing cores, the second group of two or more processing cores, or the third group of two or more processing cores to support a workflow. 
     
     
         20 . The method of  claim 12 , wherein one or more of the first group of two or more processing cores, the second group of two or more processing cores, or the third group of two or more processing cores comprises an SIMD computing array. 
     
     
         21 . The method of  claim 12 , comprising one or more of the first group of two or more processing cores, the second group of two or more processing cores, or the third group of two or more processing cores performing a dynamically configurable function. 
     
     
         22 . The method of  claim 12 , wherein one or more of the first group of two or more processing cores, the second group of two or more processing cores, or the third group of two or more processing cores comprises a processing pipeline.

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