Stack pointer value prediction

Abstract

Methods and apparatus for predicting the value of a stack pointer which store data when an instruction is seen which grows the stack. The information which is stored includes a size parameter which indicates by how much the stack is grown and one or both of: the register ID currently holding the stack pointer value or the current stack pointer value. When a subsequent instruction shrinking the stack is seen, the stored data is searched for one or more entries which has a corresponding size parameter. If such an entry is identified, the other information stored in that entry is used to predict the value of the stack pointer instead of using the instruction to calculate the new stack pointer value. Where register renaming is used, the information in the entry is used to remap the stack pointer to a different physical register.

1 . A method of predicting stack pointer values for a stack in a processor, the stack having an associated stack pointer and the method comprising, in a load-store unit in the processor:
 detecting a change in a stack pointer;   in response to detecting a change in the stack pointer, storing a register ID of a physical register storing a value of the stack pointer and the value of the stack pointer; and   
       in response to receiving an instruction to load/store using a physical register corresponding to a stored register ID, calculating an address for the load/store using the stored value of the stack pointer associated with the stored register ID. 
     
     
         2 . The method according to  claim 1 , wherein storing a register ID of a physical register storing a value of the stack pointer and the value of the stack pointer comprises:
 storing a register ID of a physical register storing a value of the stack pointer prior to the change and the value of the stack pointer prior to the change.   
     
     
         3 . The method according to  claim 1 , wherein storing a register ID of a physical register storing a value of the stack pointer and the value of the stack pointer comprises:
 storing a register ID of a physical register storing a value of the stack pointer following the change and the value of the stack pointer following the change.   
     
     
         4 . The method according to  claim 1 , wherein detecting a change in a stack pointer comprises:
 receiving notification of a change in stack pointer from a decode and rename stage in the processor.   
     
     
         5 . The method according to  claim 1 , wherein the register ID of the physical register storing the value of the stack pointer and the value of the stack pointer are stored in a stack pointer cache. 
     
     
         6 . The method according to  claim 5 , wherein the size of the stack pointer cache is limited. 
     
     
         7 . The method according to  claim 6 , wherein the register ID of the physical register storing the value of the stack pointer and the value of the stack pointer comprise a pair of values and the method further comprises:
 prior to storing the register ID of the physical register storing the value of the stack pointer and the value of the stack pointer and in response to determining that the stack pointer cache is full, discarding an oldest stored pair of values in the stack pointer cache.   
     
     
         8 . The method according to  claim 5 , further comprising:
 in response to a physical register ID being moved to a free register list, removing corresponding entries from the stack pointer cache.   
     
     
         9 . A method of predicting data values associated with a reversible function in a processor, the method comprising:
 detecting an instruction which is predicted to be reversible;   in response to detecting an instruction which is predicted to be reversible, storing a register ID of a physical register storing a value associated with the reversible function and the value stored in the physical register in a data structure; and   in response to a reverse of a previously detected reversible function, looking in the data structure for a corresponding entry and using the register identified by the stored register ID and/or the stored value in the corresponding entry.   
     
     
         10 . A processor comprising:
 a load-store unit, wherein the load-store unit is arranged:
 to detect a change in a stack pointer; 
 in response to detecting a change in the stack pointer, to store a register ID of a physical register storing a value of the stack pointer and the value of the stack pointer; and 
 in response to receiving an instruction to load/store using a physical register corresponding to a stored register ID, to calculate an address for the load/store using the stored value of the stack pointer associated with the stored register ID. 
   
     
     
         11 . The processor according to  claim 10 , wherein the processor is further arranged, in response to detecting an interrupt, to remove any entries from the data structure. 
     
     
         12 . The processor according to  claim 10 , wherein the processor is an out-of-order processor.