Semiconductor devices and methods of fabricating the same

Abstract

A semiconductor device includes a package substrate, a semiconductor chip on a first region of the package substrate, and a solder bump on a second region of the package substrate. The solder bump includes a core portion and a peripheral portion encapsulating the core portion. The peripheral portion includes a first segment with a first melting point and a second segment with a second melting point that is less than the first melting point.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a package substrate;   a semiconductor chip on a first region of the package substrate; and   a solder bump on a second region of the package substrate,   wherein the solder bump comprises:
 a core portion; and 
 a peripheral portion that encapsulates the core portion, 
   wherein the peripheral portion comprises:
 a first segment with a first melting point; and 
 a second segment with a second melting point less than the first melting point. 
   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first segment is a lower part of the solder near the package substrate and the second segment is an upper part of the solder opposite the package substrate. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the second segment envelops the core portion. 
     
     
         4 . The semiconductor device of claim,  1 , wherein the second melting point is less than the first melting point by a temperature of about 20° C. to about 120° C. 
     
     
         5 . The semiconductor device of  claim 1 , wherein a height of the solder bump is about 1 to about 1.5 times a width of the solder bump. 
     
     
         6 . The semiconductor device of  claim 1 , wherein a width of first segment is the same as or greater than a width of the second segment. 
     
     
         7 . The semiconductor device of  claim 1 , wherein a height of the core portion is less than one-fifth to one-third of a height of the solder. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the second segment has a width that decreases with increasing distance from the first segment. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the core portion has a melting point greater than the first and second melting points. 
     
     
         10 . A method for fabricating a semiconductor device, the method comprising:
 providing a lower package substrate;   forming a first solder bump on a top surface of the lower package substrate;   providing an upper package substrate including a second solder bump on a bottom surface of the upper package substrate; and   joining the first and second solder bumps to stack the lower and upper package substrates,   wherein forming the first solder bump comprises:
 forming a first solder ball on the lower package substrate, the first solder ball including a first material with a first melting point; 
 placing a second solder ball on the first solder ball, the second solder ball including a core portion and a second material encapsulating the core portion, the second material having a second melting point that is less than the first melting point; and 
 performing a first reflow process at a first temperature that is greater than the second melting point and less than the first melting point so as to join the second material to the first material. 
   
     
     
         11 . The method of  claim 10 , wherein the second solder bump comprises the second material, and
 wherein joining the first and second solder bumps comprises performing a second reflow process at a second temperature that is greater than the second melting point and less than the first melting point.   
     
     
         12 . The method of  claim 11 , further comprising, after performing the second reflow process at the second temperature, performing a third reflow process at a third temperature that is greater than the first melting point. 
     
     
         13 . The method of  claim 10 , after performing the first reflow process to join the second material to the first material, further comprising:
 forming a mold layer on the lower package substrate; and   removing portions of the mold layer to expose at least a portion of the second material.   
     
     
         14 . The method of  claim 10 , wherein the second melting point is less than the first melting point by a temperature of about 20° C. to about 120° C. 
     
     
         15 . The method of  claim 10 , wherein the first material comprises an Sn—Ag based alloy or an Sn—Cu based alloy, and the second material comprises an Sn—Pb based alloy or an Sn—Bi based alloy. 
     
     
         16 . An article comprising:
 a package substrate; and   a solder bump on the package substrate;   wherein the solder bump comprises:
 a base portion comprising a metal having a first melting point; 
 an upper portion on the base portion opposite the package substrate, the upper portion comprising a metal having a second melting point that is less than the first melting point; and 
 a core portion embedded within the upper portion, the core portion comprising a metal having a third melting point that is greater than the first melting point and the second melting point. 
   
     
     
         17 . The article of  claim 16 , wherein the second melting point is less than the first melting point by a temperature of about 20° C. to about 120° C. 
     
     
         18 . The article of  claim 16 , wherein the base portion comprises an Sn—Ag based alloy or an Sn—Cu based alloy, the upper portion comprises an Sn—Pb based alloy or an Sn—Bi based alloy, and the core portion comprises Cu. 
     
     
         19 . The article of  claim 16 , wherein the upper portion has a width that is less than a width of the base portion. 
     
     
         20 . The article of  claim 16 , wherein a height of the solder bump is about 1 to about 1.5 times a width of the solder bump.