US2017221912A1PendingUtilityA1

Semiconductor device and method of manufacturing semiconductor device

Assignee: LAPIS SEMICONDUCTOR CO LTDPriority: Nov 14, 2014Filed: Apr 13, 2017Published: Aug 3, 2017
Est. expiryNov 14, 2034(~8.3 yrs left)· nominal 20-yr term from priority
Inventors:Akira Chiba
H10P 95/062H10P 50/71H10W 20/43H01L 29/6653H01L 27/11521H01L 29/0847H01L 29/7881H01L 29/66825H01L 21/32139H01L 21/28273H01L 23/528H01L 29/42328H10D 64/035H10D 64/015H10D 62/151H10D 30/6892H10D 30/681H10D 30/0411H10B 41/00H10B 41/30
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Claims

Abstract

A method of manufacturing the semiconductor device includes forming a first gate member on a semiconductor substrate through a gate insulating film, forming a spacer on the first gate member, flattening a surface of the spacer, forming a first gate by partially etching the first gate member using the spacer as a mask, forming a second gate member so as to cover the first gate and the spacer having the flattened surface, forming a first insulating film on a surface of the second gate member, and forming a second gate by causing the second gate member to retreat while removing the first insulating film by etching, and the corresponding semiconductor device.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device comprising:
 a semiconductor substrate;   a first gate that is provided on the semiconductor substrate through a gate insulating film;   a spacer that is provided on the first gate and has a flattened surface;   a second gate that is provided on the semiconductor substrate and adjacent to the first gate and the spacer;   a source and a drain that are provided at positions between which the first gate and the second gate are interposed;   a source wiring that is electrically connected to the source; and   a metal compound layer that is provided on each of an upper surface of the second gate, an upper surface of the source wiring, and an upper surface of the drain.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein the flattened surface of the first gate is substantially parallel to the principal plane of the semiconductor substrate.

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