Solar cell emitter region fabrication with differentiated p-type and n-type region architectures

Abstract

Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.

What is claimed is: 
     
         1 . A method of fabricating alternating N-type and P-type emitter regions of a solar cell, the method comprising:
 forming a first silicon layer of a first conductivity type on a first thin dielectric layer formed on a back surface of a substrate;   forming an insulating layer on the first silicon layer;   patterning the insulating layer and the first silicon layer to form first silicon regions of the first conductivity type having an insulating cap thereon;   forming a second thin dielectric layer on exposed sides of the first silicon regions;   forming a second silicon layer of a second, different, conductivity type on a third thin dielectric layer formed on the back surface of the substrate, and on the second thin dielectric layer and the insulating cap of the first silicon regions;   patterning the second silicon layer to form isolated second silicon regions of the second conductivity type and to form contact openings in regions of the second silicon layer above the insulating cap of the first silicon regions;   patterning the insulating cap through the contact openings to expose portions of the first silicon regions;   forming a mask to expose only the exposed portions of the first silicon regions and the isolated second silicon regions;   forming a metal seed layer on the exposed portions of the first silicon regions and on the isolated second silicon regions; and   plating a metal layer on the metal seed layer to form conductive contacts for the first silicon regions and the isolated second silicon regions.