Techniques for entering a low power state

Abstract

Various embodiments are generally directed to an apparatus, method and other techniques for initiating a transition into a lower power state, determining that a device process prevents a platform processing device from completing the transition to the lower power state and interrupting a processing component from an intermediate power state in order to process the process prior to execution of a defined event.

What is claimed is: 
     
         1 . An apparatus, comprising:
 a platform processing device comprising a processor component and a power management component, the power management component to initiate a transition into a lower power state and determine that a device process prevents the platform processing device from completing the transition to the lower power state, the power management component to interrupt the processor component from an intermediate power state in order to process the device process prior to execution of a defined event.   
     
     
         2 . The apparatus of  claim 1 , the device process to comprise a software process or an autonomous hardware process, and the power management component to determine when the software process or autonomous hardware process prevents the platform processing device from transitioning into the low power state. 
     
     
         3 . The apparatus of  claim 1 , the power management component to wait a platform specific timer period before interrupting the processor component. 
     
     
         4 . The apparatus of  claim 1 , the power management component to determine which of a platform specific time period or a software ready time period is longer and to wait the longer of the platform specific time period or the software ready time period before interrupting the processor component. 
     
     
         5 . The apparatus of  claim 4 , the defined event comprising a defined interrupt or an expiration of a timer, the defined event to occur after the expiration of the platform specific time period and the software ready time period. 
     
     
         6 . The apparatus of  claim 4 , the software ready time period to indicate when a software process can process a task and the platform specific time period to indicate when autonomous hardware processes are complete. 
     
     
         7 . The apparatus of  claim 1 , the power management component to wait for one or more autonomous hardware processes to complete and to transition the platform processing device to the lower power state when the one or more autonomous hardware processes are complete. 
     
     
         8 . The apparatus of  claim 1 , the processor component to execute the process that prevents the apparatus from entering the lower power state, and notify the platform processing device to enter into the lower power state upon completion of execution. 
     
     
         9 . The apparatus of  claim 1 , the power management component to determine when the process prevents entry into the lower power state when the platform processing device does not enter the low power state upon expiration of a platform specific time period or completion of processing of one or more autonomous hardware processes. 
     
     
         10 . An article comprising a computer-readable storage medium containing a plurality of instructions that when executed enable a processor to:
 initiate a transition into a lower power state;   determine that a device process prevents a system from completing the transition to the lower power state; and   interrupt the processor from an intermediate power state in order to process the device process prior to execution of a defined event.   
     
     
         11 . The article of  claim 10 , the device process to comprise a software process or an autonomous hardware process and the plurality of instructions that when executed by the processor enable the system to determine when the software process or autonomous hardware process prevents the system from transitioning into the low power state. 
     
     
         12 . The article of  claim 10 , comprising the computer-readable storage medium containing the plurality of instructions that when executed enable the processor to wait a platform specific timer period before interrupting the processor component. 
     
     
         13 . The article of  claim 10 , comprising the computer-readable storage medium containing the plurality of instructions that when executed enable the processor to:
 determine which of a platform specific time period or a software ready time period is longer; and   wait the longer of the platform specific time period or the software ready time period before interrupting the processing component.   
     
     
         14 . The article of  claim 10 , comprising the computer-readable storage medium containing the plurality of instructions that when executed enable the processor to:
 wait for one or more autonomous hardware processes to complete; and transition the platform processing device to the lower power state when the one or more autonomous hardware processes are complete.   
     
     
         15 . The article of  claim 10 , comprising the computer-readable storage medium containing the plurality of instructions that when executed enable the processor to:
 execute the process preventing the system from entering the lower power state; and   enter the lower power state upon completion of the process.   
     
     
         16 . The article of  claim 10 , comprising the computer-readable storage medium containing the plurality of instructions that when executed enable the processor to:
 determine when the process prevents entry into the lower power state and when the system does not enter the low power state upon expiration of a platform specific time period or completion of processing of one or more autonomous hardware processes.   
     
     
         17 . A controller, comprising logic at least a portion of which is in hardware, the logic to:
 initiate a transition into the lower power state and determine that a device process prevents the platform processing device from completing the transition to the lower power state, interrupt the processor component from an intermediate power state in order to process the device process prior to execution of a defined event.   
     
     
         18 . The controller of  claim 17 , the device process to comprise a software process or an autonomous hardware process, and the logic to determine when the software process or autonomous hardware process prevents the platform processing device from transitioning into the low power state. 
     
     
         19 . The controller of  claim 17 , the logic to wait a platform specific timer period before interrupting the processor component. 
     
     
         20 . The controller of  claim 17 , the logic to determine which of a platform specific time period or a software ready time period is longer and the logic to wait the longer of the platform specific time period or the software ready time period before interrupting the processor component. 
     
     
         21 . The controller  claim 20 , the defined event comprising a defined interrupt or an expiration of a timer, the defined event to occur after the expiration of the platform specific time period and the software ready time period. 
     
     
         22 . The controller of  claim 21 , the software ready time period to indicate when a software process can process a task and the platform specific time period to indicate when autonomous hardware processes are complete. 
     
     
         23 . The controller of  claim 17 , the logic to wait for one or more autonomous hardware processes to complete and to transition the platform processing device to the lower power state when the one or more autonomous hardware processes are complete. 
     
     
         24 . The controller of  claim 17 , the logic to execute the process that prevents the apparatus from entering the lower power state, and to notify the platform processing device to enter into the lower power state upon completion of execution. 
     
     
         25 . The controller of  claim 17 , the logic to determine when the process prevents entry into the lower power state when the platform processing device does not enter the low power state upon expiration of a platform specific time period or completion of processing of one or more autonomous hardware processes.