Test apparatus and semiconductor chip

Abstract

A test apparatus may be provided. The test apparatus may include a delay compensator configured to generate delayed read data by delaying read data according to a difference between an external turnaround delay value provided externally from the test apparatus and a turnaround delay detection value detected within the test apparatus. The test apparatus may include a determination circuit configured to perform a test result determination operation by comparing the delayed read data with reference data. The turnaround delay detection value may be generated by detecting a time of from a point of time when write data including a read command as the reference data is output to a point of time when the read data is received.

What is claimed is: 
     
         1 . A test apparatus comprising:
 a delay compensator configured to generate delayed read data by delaying read data according to a difference between an external turnaround delay value provided externally from the test apparatus and a turnaround delay detection value detected within the test apparatus; and   a determination circuit configured to perform a test result determination operation by comparing the delayed read data with reference data,   wherein the turnaround delay detection value is generated by detecting a time of from a point of time when write data including a read command as the reference data is output to a point of time when the read data is received.   
     
     
         2 . The test apparatus of  claim 1 , wherein the test apparatus is coupled to a first channel and a second channel,
 the test apparatus further comprising:   a first path circuit configured to transmit the write data to the first channel; and   a second path circuit configured to transmit the read data transmitted through the second channel to the delay compensator.   
     
     
         3 . The test apparatus of  claim 2 , wherein the first path circuit includes:
 a serializer configured to serialize the write data and output serialized write data; and   a transmitter configured to transmit an output of the serializer to the first channel.   
     
     
         4 . The test apparatus of  claim 2 , wherein the second path circuit includes:
 a receiver configured to receive the read data; and   a parallelizer configured to parallelize an output of the receiver and transmit the parallelized output of the receiver to the delay compensator.   
     
     
         5 . The test apparatus of  claim 1 , wherein the delay compensator includes:
 a delay circuit configured to generate a plurality of delay signals by delaying the read data;   a multiplexer configured to select one among the plurality of delay signals and output the selected delay signal as the delayed read data according to a control signal;   a period signal generator configured to generate a period signal according to a calibration enable signal, the write data, and the read data; and   a controller configured to generate the turnaround delay detection value according to the period signal and a clock signal and generate the control signal according to the external turnaround delay value and the turnaround delay detection value.   
     
     
         6 . The test apparatus of  claim 5 , wherein the period signal generator includes:
 a first logic gate configured to generate a first period signal according to the calibration enable signal and the write data; and   a second logic gate configured to generate a second period signal according to the calibration enable signal and the read data.   
     
     
         7 . The test apparatus of  claim 5 , wherein the controller includes:
 a latch configured to generate a counting enable signal according to the period signal;   a counter configured to output a counting value of the clock signal as the turnaround delay detection value according to the counting enable signal; and   an operator configured to output an operation result value for a difference between the external turnaround delay value and the turnaround delay detection value as the control signal.   
     
     
         8 . The test apparatus of  claim 5 , wherein the delay circuit includes a plurality of flip flops configured to shift the read data or an output of a previous flip flop according to the clock signal. 
     
     
         9 . A test apparatus comprising:
 a tester configured to set a delay compensation time of read data by detecting a turnaround delay of from a first point of time when write data including a read command is output in a turnaround delay compensation mode to a second point of time when the read data received exteriorly from the test apparatus is received, generate delayed read data by delaying the read data by the delay compensation time in a normal test mode, and perform a test result determination operation by comparing the delayed read data with the write data as reference data.   
     
     
         10 . The test apparatus of  claim 9 , wherein the tester enters the turnaround delay compensation mode by activating a calibration enable signal. 
     
     
         11 . The test apparatus of  claim 9 , wherein the tester enters the normal test mode by inactivating the calibration enable signal. 
     
     
         12 . The test apparatus of  claim 9 , wherein the tester includes:
 a delay circuit configured to generate a plurality of delay signals by delaying the read data;   a multiplexer configured to select one of the plurality of delay signals and output the selected delay signal as the delayed read data according to a control signal;   a period signal generator configured to generate a period signal which defines a period of from the first point of time to the second point of time according to a calibration enable signal, the write data, and the read data; and   a controller configured to generate a turnaround delay detection value corresponding to the turnaround delay according to the period signal and a clock signal and generate the control signal according to an external turnaround delay value and the turnaround delay detection value.   
     
     
         13 . The test apparatus of  claim 12 , wherein the delay circuit includes a plurality of flip flops configured to shift the read data or an output of a previous flip flop according to the clock signal. 
     
     
         14 . The test apparatus of  claim 12 , wherein the period signal generator includes:
 a first logic gate configured to generate a first period signal activated at the first point of time according to the calibration enable signal and the write data; and   a second logic gate configured to generate a second period signal activated at the second point of time according to the calibration enable signal and the read data.   
     
     
         15 . The test apparatus of  claim 12 , wherein the controller includes:
 a latch configured to generate a counting enable signal according to the period signal;   a counter configured to output a counting value of the clock signal as the turnaround delay detection value according to the counting enable signal; and   an operator configured to output an operation result value for a difference between the external turnaround delay value and the turnaround delay detection value as the control signal.   
     
     
         16 . The test apparatus of  claim 9 , wherein the test apparatus is coupled to a first channel and a second channel,
 the test apparatus further comprising:   a first path circuit configured to transmit the write data to the first channel; and   a second path circuit configured to transmit the read data transmitted through the second channel to the tester.   
     
     
         17 . The test apparatus of  claim 16 , wherein the first path circuit includes:
 a serializer configured to serialize the write data and output serialized write data; and   a transmitter configured to transmit an output of the serializer to the first channel.   
     
     
         18 . The test apparatus of  claim 16 , wherein the second path circuit includes:
 a receiver configured to receive the read data; and   a parallelizer configured to parallelize an output of the receiver and transmit the parallelized output of the receiver to the tester.   
     
     
         19 . A test apparatus for a semiconductor chip, the test apparatus comprising:
 a delay compensator configured to generate delayed read data by delaying read data according to a difference between an external turnaround delay value provided externally from the test apparatus and a turnaround delay detection value detected within the test apparatus; and   a determination circuit configured to perform a test result determination operation by comparing the delayed read data with reference data,   wherein the turnaround delay detection value is generated by detecting a time of from a point of time when write data including a read command as the reference data is output to the semiconductor chip to a point of time when the read data is input from the semiconductor chip.