Multi-chip package and manufacturing method

Abstract

Manufacturing method and a multi-chip package, which comprises a conductor pattern and insulation, and, inside the insulation, a first component, the contact terminals of which face towards the conductor pattern and are conductively connected to the conductor pattern. The multi-chip package also comprises inside the insulation a second semiconductor chip, the contact terminals of which face towards the same conductor pattern and are conductively connected through contact elements to this conductor pattern. The semiconductor chips are located in such a way that the first semiconductor chip is located between the second semiconductor chip and the conductor pattern.

1 . A multi-chip package comprising:
 a conductor pattern;   a first component and a second component both embedded in an insulation such that the first component is located between the conductor pattern and the second component;   the first component and the second component both comprising contact terminals facing towards the conductor pattern; and   contact elements between the contact terminals of the second component and the conductor pattern, the contact elements containing electrochemically grown copper;   wherein the contact terminals of the second component are electrically connected to the conductor pattern over conductor paths each running through one of said contact elements.   
     
     
         2 . The multi-chip package of  claim 1 , wherein the first component is a microprocessor and the second component is a memory. 
     
     
         3 . The multi-chip package of  claim 1 , wherein the contact elements extend between the contact terminals of the second component and the conductor pattern principally only in the thickness direction of the multi-chip package. 
     
     
         4 . The multi-chip package of  claim 1 , wherein the first component is located entirely between the second component and the conductor pattern. 
     
     
         5 . The multi-chip package of  claim 1 , wherein the contact elements are mainly formed of copper. 
     
     
         6 . The multi-chip package of  claim 5 , wherein the contact elements have a height, the height being in the range of 10 to 200 micrometres. 
     
     
         7 . The multi-chip package of  claim 1 , wherein the conductor pattern is in one planar layer in the multi-chip package. 
     
     
         8 . The multi-chip package of  claim 7 , comprising further conductor patterns in further planar layers in the multi-chip package, wherein the conductor patterns are separated from each other by insulator in the thickness direction of the multi-chip package. 
     
     
         9 . A multi-chip package comprising:
 a planar conductor pattern;   a first component embedded in an insulation on the planar conductor pattern, the first component having first contact terminals facing towards the planar conductor pattern and conductively connected to the planar conductor pattern by means of first contact elements; and   a second component embedded in the insulation on the planar conductor pattern such that the first component is located between the second component and the planar conductor pattern, the second component having second contact terminals facing towards the planar conductor pattern and conductively connected to the planar conductor pattern by means of second contact elements, each second contact element comprising a metal core made of electrochemically grown copper.   
     
     
         10 . The multi-chip package of  claim 9 , wherein the first component is a microprocessor and the second component is a memory. 
     
     
         11 . The multi-chip package of  claim 10 , wherein the microprocessor is located entirely between the memory and the planar conductor pattern. 
     
     
         12 . The multi-chip package of  claim 9 , wherein each first contact element comprises at least one layer of electrochemically grown copper. 
     
     
         13 . The multi-chip package of  claim 9 , wherein the second contact elements extend between the contact terminals of the second component and the planar conductor pattern principally only in the thickness direction of the multi-chip package. 
     
     
         14 . The multi-chip package of  claim 13 , wherein the second contact elements have a height in the thickness direction of the multi-chip package, the height being in the range of 10 to 200 micrometres. 
     
     
         15 . The multi-chip package of  claim 9 , wherein at least one first contact terminal is electrically connected to at least one second contact terminal over a conductor path, which conductor path consists of part of the planar conductor pattern as well as one of the first contact elements and one of the second contact elements. 
     
     
         16 . The multi-chip package of  claim 9 , wherein each second contact element is a cylindrical conductor piece. 
     
     
         17 . A multi-chip package comprising:
 a conductor pattern;   a microprocessor and a memory embedded in the multi-chip package such that the microprocessor is located between the conductor pattern and the memory, the microprocessor and the memory both comprising contact terminals facing towards the conductor pattern;   first contact elements between the conductor pattern and the contact terminals of the microprocessor;   second contact elements between the conductor pattern and the contact terminals of the memory, each second contact element made of copper and having a height of 10 to 200 micrometres.   
     
     
         18 . The multi-chip package of  claim 17 , wherein each second contact element has a width of 10 to 200 micrometres. 
     
     
         19 . The multi-chip package of  claim 18 , wherein the second contact elements extend between the conductor pattern and the contact terminals of memory principally only in the thickness direction of the multi-chip package. 
     
     
         20 . The multi-chip package of  claim 17 , wherein the microprocessor is located entirely between the memory and the conductor pattern.